* Index ==============================================================
Wed Sep 6 00:47:28 PDT 1995 - Created the 32-bit comparator component
Thu Sep 7 14:02:21 PDT 1995 - Tested the comparator
Mon Sep 11 12:01:45 PDT 1995 - Investigated bug found by Bart in
comp32 and fixed it
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Wed Sep 6 00:47:28 PDT 1995
Goal: Layout the schematic for a 32-bit comparator
I've layed out the schemtatics and made a symbol for the comparator.
I named it comp32. The files are
~/wv/proj1/sch/comp32.sch
~/wv/proj1/sch/comp32.sym
Wed Sep 6 02:29:22 PDT 1995
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Thu Sep 7 14:02:21 PDT 1995
Goal: Test the comparator component
I've written a command file to test comp32. I've placed it
in ~/wv/proj1/diagnostics/comp32.cmd.
I ran the command file in viewsim and it looks like the comparator
is working fine. I saved the output into a log file called
~/wv/proj1/diagnostics/comp32.log
Notified the rest of the group that the comparator
is done.
Thu Sep 7 16:15:32 PDT 1995
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Mon Sep 11 12:01:45 PDT 1995
Goal: Investigate bug discovered in comp32 and hopefully fix it
Bart found a bug in my comparator component.. He left the following
e-mail..
-------------------
Hey Bruce,
I think there's a bug in your comparator..
Can you take a look at this?
Bart
I verified the bug.. here's a viewsim of the bug as it appeared..
Ah.. I've discovered the bug.. I mislabeled the 4th net in
I corrected the mistake and re-checked all the other
I re-ran the old diagnostic test file and tested it against
On second inspectation of the whole layout, I think I can
I e-mailed the group that the bug has been fixed
Mon Sep 11 14:03:41 PDT 1995
From bart@simpsons.residence Sun Sep 10 01:47:02 1995
Received: by wayne.manor (NX5.67e/NX3.0S)
id AA00334; Sun, 10 Sep 95 01:47:01 -0800
Date: Wed, 10 Sep 95 01:47:01 -0800
From: Bart Simpson
To: bruce@wanye.manor, old_man@gokuraku, hojo@sanctuary
Subject: [cs152] bug in comp32
Status: R
The comparator seems to think that ffffffff and fffffff7 are equal..
------------------
(equal should be 0 instead of 1)
------------------
SIM>stepsize 10ns
SIM>v a_in A[31:0]
SIM>v b_in B[31:0]
SIM>w a_in b_in equal
SIM>a a_in ffffffff\h
SIM>a b_in fffffff7\h
SIM>sim
time = 10.0ns A_IN=FFFFFFFF\H B_IN=FFFFFFF7\H EQUAL=1
Simulation stopped at 10.0ns.
-------------------
the comp32 schematic..
labels, just in case.
the bug Bart found... it seems to be working fine.. hopefully
there isn't any more bugs..
remove one level of gates in the design and make it go faster..
But who cares.. the comparator is not in the critical path
right now.. the delay through the ALU is dominating the critical
path.. so unless the ALU gets a lot faster, we can live with
a less than optimal comparator..
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