CS 61C Homework 3-1

Background reading

Lecture notes from 7/6 and P&H: Chapters 3.4, 3.8

Administrative requirements

Submit your solution online by 8pm on the 11th of July, 2004. Do this by creating a directory named hw3-1 that contains the files hw3-1.txt (put your answers to problems 1 and 2 in here), and lowerCase.s (problem 3 solution). From within that directory, type:

submit hw3-1

This is not a partnership assignment -- hand in your own work, and don't collaborate with anyone else.

Problem 1: Warm Up

P&H exercises 3.3, 3.4, 3.7, 3.8

Problem 2: Assembly to Machine Language

Fill in the table below for the following instructions. Under the field names (op, rd, rs, address, etc...) put the value for that particular instruction. If a particular field does not apply to an instruction, then write "n/a". That means that you do not need to worry about overlapping fields; fill in only the fields that are used by the processor for that particular instruction. You may find the table in the back of P&H to be helpful. Assume that L1 is at address 0x00400000, L2 is at address 0x00400030, and L3 is at address 0x00400FF0. The first line is done for you.

	L1:
	1	add	$1, $2, $0
	2	addi	$3, $4, 5
	3	sll	$1, $9, 5
	4	lw	$4, 0($31)
	5	sw	$1, 6($31)
	6	beq	$1, $26, L2
	7	j	L3

Line	Format	op	rs	rt	rd	shamt	funct	immed	address
1	R	0	2	0	1	0	32	n/a	n/a

Now translate these same instructions into MIPS machine language. Write your answers in hexadecimal. Again, the first one is done for you. You can use the web based MIPSASM to check your answers.

	1	0x00400820

Problem 3: Disassembling Machine Language

Given the following MIPS machine language instructions, translate them back to MIPS assembly and state their format (R, I, J):

The first instruction is located at address 0x00400000 and the others follow in sequence. You may leave your registers as numbers (you don't need to use names $s0, $t0, $sp, etc...). For jumps and branches, state the absolute address of the target. You must show a table similar to the one in problem 2 to receive full credit!

Problem 4: Modifying the instruction set

When a new processor is designed to the specifications of an existing architecture family, one of the requirements is backwards compatibility of binary executables. This means that binaries compiled for the old processor will still execute faithfully on the new processor. That is, code compiled for an Intel 386 will still run on a Pentium. Now imagine that you are designing the instruction set for a new MIPS processor that will have 64 CPU registers instead of the current 32. How might you modify the existing MIPS R-format instruction layout to be able to address all 64 registers from each of the 3 register fields while still maintaining the ability to run regular MIPS code? Instructions are still 32 bits long. Shift operations (sll, srl, sra) do not need this new ability. Remember that all existing instructions (not just R-format) need to be accessible.