CS61C Summer 2004

Homework Assignment for week 5-1

A MIPS Subset CPU

updated on July 21

Administrative:

Please note, this homework is rather long, but it is intended to help you directly with your next project.  Start early!

Important note: Your ALU and control modules have to be implemented in structural verilog, The regfile and testbench files can be written in behavioral verilog.

This homework is due on Sunday July 25, before midnight. To submit, create a folder hw5-1, containing the following files:

cpu.v

regfiletest.v

ALUtest.v

controltest.v

Reading:

This homework will give you a better sense of the datapath. To prepare for the homework you can read through chapter 5 of the COD (by P&H). Section 5.2 shows you a step by step breakdown of the datapath. Look for the explanations on the Registers and ALU modules and R-type instructions in this section. Section 5.3 has useful information on the control unit, and the ALU control. Appendix C of the COD and more specifically C.2 is a good reference for designing your control unit. Use lecture notes on CPU Design II (lec5-1-2) for the implementation of the regfile.

Exercise 0:  regfile (10 points)

Part a) Create module regfile,  using the registers file described in lecture 5-1-2, and add it to the file cpu.v.

Your regfile should hold an array of 32 registers, each 32-bits wide. It should be able to read from and write into the appropriate register in the array, depending on the control signals.

Part b) Next write a testbench in the file regfiletest.v that tests your regfile as thoroughly as possible.

Exercise 1:  ALU (30 points)

Part a) Implement a simple version of ALU module in structural verilog, which is capable of addition, subtraction, testing for equality and nonequality, and comparison between two numbers. Add this module your cpu.v file.

Inputs: 2 ports of width 32 each A and B, and the appropriate control signals.

Outputs: 1 port of width 32 to hold the result of the ALU operations add, sub and slt, one  port of a single wire to signal whether the equality or non equality is true or false, with 0 representing false, and 1 true.

Part b) Write a testbench to test your ALU, in ALUtest.v

Exercise 2:  control (30 points)

Part a) Design a control unit and add it to the cpu.v, which takes in and decodes the 32-bit wide instruction and sends control signals to regfile and ALU. Your control unit should recognize the following subset of MIPS instructions:

add, sub, slt, beq, and bne

You do not need to have a PC, nor do you need to handle any changes to the PC for the branch instructions. In other words, for your homework, the beq and bne only send a signal saying if the condition was true or false, but they do not actually branch. Considering this, notice you will not need to handle an immediate field for any of the instructions in this subset.

Part b) As you would do for any module you write in verilog, write a testbench that tests the control unit you have implemented. You need to test the controller with at least one instance of each of the supported instructions in this subset of MIPS. This modules goes into controltest.v 

Exercise 3:  everything together (30 points)

Part a) Write a module called CPU that connects the regfile, ALU and the control unit together, creating a simple datapath. To help you visualize the connections, you are encouraged to draw a schematic version first.

Part b) Write a driver module that tests your CPU with several instructions. Put both the driver and the CPU in the same cpu.v file.