CS61c, Summer 2004

Homework 5-2 Pipelined MIPS

Administrative:

      This homework is designed to take less than 1 hour to complete. Be precise in your answers, the homework will be graded based on exactness. Type your answers in a text file called hw5-2.txt and submit by copying the file into a directory called hw5-2 and type

submit hw5-2

from within the directory. The homework is due before midnight of Sunday July 25^th.

a)      Identify which of the following data dependencies are data hazards, then explain how they are resolved in MIPS architecture.

Read after Write (RAW):

Write after Read (WAR):

Write after Write (WAW):

Read after Read (RAR):

For questions b) through e) consider executing the following code in the 5-stage pipelined datapath as discussed in lecture and the COD book, which includes all the possible data forwarding.

10 add $2, $5, $4

            20 add $4, $2, $5

            30 sw   $5, 100($2)

            40 add $3, $2, $4

            50 lw   $5, 0($2)

            60 add $4, $2, $5

            70 beq $5, $4, L

b)      Identify all of the data dependencies (mention the type of dependency). Which dependencies are data hazards that will be resolved via forwarding?

c)      Rewrite the code and add no op instructions (sll $0, $0, 0) wherever the forwarding does not resolve the data hazard.

d)      How many cycles will it take to execute the code.

e)      At the end of the 5^th cycle of execution, which registers are being read and which register will be written?

f)    Explain briefly why unrolling loops might gain performance in executing the code in a pipelined CPU.