#! /usr/bin/perl

use Getopt::Long;
use POSIX qw(ceil floor);

$VERSION = "v0.91";

$USAGE = '  Command Line Options:
    -v[erbose]             -- Optional; Print helpful info to stdout
    -d[ebug]               -- Optional, Print lots of stuff to stdout
    -h[elp]                -- Optional; Print help on 
    -i[nputfile]           -- File that contains MIPS assembly
    -o[outputfile]         -- File in which to write machine code
    -c[onfigfile]          -- File that hold configuration options
    -m[odulename]          -- Name of verilog module to create. Overrides config file.
    -r[amtype]             -- Type of ram to create. Overrides config file. See config for help
  Usage:
    hex2mem [-v] [-d] [-c <filename>] [-m <modulename] [-r <ramtype] -i <filename> -o <filename> 
';

do_load_defaults();
do_get_args();
#do_load_config();
do_open_files();
#do_setup_hashes();
do_print_verilog();
exit(0);

sub do_load_defaults() {
    #Used if not overridden
    $OP_MODULE   = "instmem";
    $OP_NUMPORTS = "1";
    $OP_SYNREAD  = "sync";
    $OP_SYNWRITE = "sync";
    $OP_SYNRESET = "sync";
    $VERBOSE = 0;   $DEBUG = 0;
    $IN_FILE = 0;   $OUT_FILE = 0;
}

sub do_get_args() {

    $num_args = $#ARGV;
    $ops = GetOptions("verbose" => \$VERBOSE,
		      "debug" => \$DEBUG,
		      "help" => \$need_help,
		      "inputfile=s" => \$IN_FILE,
		      "outputfile=s" => \$OUT_FILE,
		      "configfile=s" => \$CONFIG_FILE,
		      "ramtype=s"    => \$temp,
		      "modulename=s" => \$OP_MODULE);

    if ($need_help == 1) {
	print_help();
	exit(0);
    } elsif ($ops == 0 || $num_args < 3) {
	print $USAGE;
	exit(0);
    } elsif ($DEBUG) {
	$VERBOSE = 1;
    }

    if ($temp ne "") {
	$OP_NUMPORTS = 1 if ($temp =~ /singleport/);
	$OP_NUMPORTS = 2 if ($temp =~ /dualport/);

	$OP_SYNREAD = "sync" if ($temp =~ /syncread/);
	$OP_SYNREAD = "async" if ($temp =~ /asyncread/);

	$OP_SYNWRITE = "sync" if ($temp =~ /syncwrite/);
	$OP_SYNWRITE = "async" if ($temp =~ /asyncwrite/);

	#fixme: reset?
    }

    print "[*] Starting hex2mem:\n" if $VERBOSE;
    print "     Options: verbose=$VERBOSE debug=$DEBUG " .
	  "inputfile=$IN_FILE outputfile=$OUT_FILE\n" .
	  "     ports=$OP_NUMPORTS read=$OP_SYNREAD ". 
	  "write=$OP_SYNWRITE reset=$OP_SYNRESET\n" if $VERBOSE;
}

sub do_open_files() {
    if (!(-e $IN_FILE)) {
	die "Cannot find input file \"$IN_FILE\"\n";
    } elsif (!open(IN, "<$IN_FILE")) {
	die "Cannot open input file \"$IN_FILE\": $!\n";	
    }
    if (!open(OUT, ">$OUT_FILE")) {
	die "Cannot open input file \"$OUT_FILE\": $!\n";	
    }
}

sub do_print_verilog() {
    if ($OP_NUMPORTS == 1 and $OP_SYNREAD eq "sync" and $OP_SYNWRITE eq "sync") {
	do_parse_8x16x16();
	do_write_single_sync_sync();
    } elsif ($OP_NUMPORTS == 1 and $OP_SYNREAD eq "async" and $OP_SYNWRITE eq "sync") {
	do_parse_4x32x1();
	do_write_single_async_sync();
    } else {
	print "ERROR: Your ram configuration is not yet implemented.\n";
	exit(0);
    }

    print "[*] hex2mem RAM Module Completed! Output written to \"$OUT_FILE\".\n" if $VERBOSE;

}


sub do_parse_8x16x16() {
    print "     Loading input lines and sorting into ram blocks and lines\n" .
	"       8 blocks of 16 lines of 256 bits divided into high-16 and low-16\n" .
	"      Legend: \"v\" means a value was found in input file and will be stored.\n" .
	"              \"0\" means no value, so mem word will be initialized to 0\n" .
	"              Most significant word is on the left.\n"
	if $VERBOSE;

    print "     Run with -d option to see table (it's big!)\n" if $VERBOSE && !$DEBUG;

    @memarrayhigh;
    @memarraylow;
    $input_line_number = 0;
    for ($block = 0; $block < 8; $block++) {
	for ($line = 0; $line < 16; $line++) {
	    print "      [block $block line $line] " if $DEBUG; 
	    $temph = "";
	    $templ = "";
	    $display = "";
	    for ($word = 0; $word < 16; $word++) {   #was $word < 8 KURT OK
		$input = <IN>;
		$input_line_number++;
		chomp($input);
		if ($input =~ /^([0123456789abcdefABCDEF]{4})([0123456789abcdefABCDEF]{4})$/) {
		    $temph = $1 . $temph;
		    $templ = $2 . $templ;
		    #print "v" if $DEBUG;
		    $display = "v" . $display;
		} elsif ($input eq "") {
		    $temph = "0000" . $temph;
		    $templ = "0000" . $templ;
		    #print "0" if $DEBUG;
		    $display = "0" . $display;
		} else {
		    print "ERROR: Found invalid value at line $input_line_number: $input\n";
		    print "       (Must be an 8-digit hex value - use mipsasm!)\n";
		    exit(0);
		}
	    }
	    $memarrayhigh[$block][$line] = $temph;
	    $memarraylow[$block][$line] = $templ;
	    print "$display: $temph:$templ\n" if $DEBUG;
	    #print "\n" if $DEBUG;
	}
    }
}

sub do_parse_4x32x1() {
    print "     Loading input lines and sorting into ram blocks and lines\n" .
	"       4 sets of 32 blocks of 32 bits striped bitwise column-major\n" .
	"      Legend: \"v\" means a value was found in input file and will be stored.\n" .
	"              \"0\" means no value, so mem word will be initialized to 0\n" .
	"              Most significant word is on the left.\n"
	if $VERBOSE;

    print "       Run with -d option to see table (it's big!)\n" if $VERBOSE && !$DEBUG;

    @memarray;
    @temp;
    $input_line_number = 0;

    for ($set = 0; $set < 4; $set++) {
	print "      [set $set] : " if $DEBUG;
	for ($line = 0; $line < 32; $line++) {
	    $input_line_number++;
	    $display = "";
	    $input_orig = <IN>;
	    chomp($input_orig);

	    if ($input_orig =~ /^[0123456789abcdefABCDEF]{8}$/) {
		#ok, found a val.
		$display = "v";
	    } elsif ($input_orig eq "") {
		$input_orig = "00000000";
		$display = "0";
	    } else {
		print "ERROR: Found invalid value at line $input_line_number: $input_orig\n";
		print "       (Must be an 8-digit hex value - use mipsasm!)\n";
		exit(0);
	    }
	    $input_bin = hextobin($input_orig);
	    @temp = split(//, $input_bin);

	    #print "Replacing $input_orig with $input_bin\n" if $DEBUG;
	    
	    for ($bit = 0; $bit < 32; $bit++) {
		$memarray[($set * 32) + (31 - $bit)][$line] = $temp[$bit];
	    }
	    $input_line_number++;
	    print $display if $DEBUG;
	}
	print "\n" if $DEBUG;
    }

    if ($DEBUG) {
	print "     Output bit pattern:\n";
	for ($i = 0; $i < 128; $i++) {
	    print "      [line $i] "; 	
	    for ($j = 31; $j > -1; $j--) {
		print $memarray[$i][$j];
	    }
	    print "\n";
	}
    }
}

sub hextobin() {
    local $line = shift();
    $line =~ s/0/xxxx/g;
    $line =~ s/1/xxxy/g;
    $line =~ s/2/0010/g;
    $line =~ s/3/0011/g;
    $line =~ s/4/0100/g;
    $line =~ s/5/0101/g;
    $line =~ s/6/0110/g;
    $line =~ s/7/0111/g;
    $line =~ s/8/1000/g;
    $line =~ s/9/1001/g;
    $line =~ s/[aA]/1010/g;
    $line =~ s/[bB]/1011/g;
    $line =~ s/[cC]/1100/g;
    $line =~ s/[dD]/1101/g;
    $line =~ s/[eE]/1110/g;
    $line =~ s/[fF]/1111/g;
    $line =~ tr/[x, y]/[0, 1]/;
    return $line;
}

sub do_write_single_async_sync() {
    $foo = <<ENDWAS1;

//----------------------------------------------------------------------
//
// Autogenerated Verilog RAM Module - Created by hex2mem $VERSION
//
// Specs:
//  128 Words Total Size
//     1-Word Block Striped
//   
//  Single Ported
//  ASYNCHRONOUS reads, 
//  Synchronous writes
// 

`timescale 1ns / 1ps

module manualram(clk,addr,din,dout,we);
    input clk;
    input [6:0] addr;
    input [31:0] din;
    input we;
    output [31:0] dout;
    reg [31:0] dout;

    wire [127:0] outw;
    reg [3:0] wew;

ENDWAS1

for ($i = 0; $i < 128; $i++) {
 $din = $i % 32;
 $wen = floor ($i / 32);
 $foo = $foo . "    RAM32X1S a_ram$i (.WCLK(clk), .D(din[$din]), .O(outw[$i]), .WE(wew[$wen]),.A4(addr[4]), .A3(addr[3]), .A2(addr[2]), .A1(addr[1]), .A0(addr[0]));\n";
}

$foo = $foo . "\n";

for ($i = 0; $i < 128; $i++) {
 $foo = $foo . "    defparam a_ram$i.INIT = 32'b";
 for ($j = 31; $j > -1; $j--) {
  $foo = $foo . $memarray[$i][$j];
 }
 $foo = $foo . ";\n";
}

$foo = $foo . <<ENDWAS2;

   // The output mux
   always @ (*)
   begin
   	case (addr[6:5])
   		2'b00: dout <= outw[31:0];
      		2'b01: dout <= outw[63:32];
      		2'b10: dout <= outw[95:64];
       		2'b11: dout <= outw[127:96];
       	endcase
   end

   // The input decoder
   always @ (*)
   begin
   	if(we)
       	begin
      		case(addr[6:5])
     			2'b00: wew <= 4'b0001;
       			2'b01: wew <= 4'b0010;
       			2'b10: wew <= 4'b0100;
       			2'b11: wew <= 4'b1000;
      		endcase
       	end
       	else
       	begin
       		wew <= 4'b0000;
       	end
   end

endmodule


ENDWAS2

print OUT $foo;
print $foo if $DEBUG;
}




sub do_write_single_sync_sync() {
    $foo = <<ENDWSS;

//----------------------------------------------------------------------
//
// Autogenerated Verilog RAM Module - Created by hex2mem $VERSION
//
// Specs:
//  2048 Words Total Size
//     8 Word Blocks
//  Single Ported
//  Synchronous reads, writes, reset
// 

`timescale 1ns / 1ps

module $OP_MODULE (addr, clk, di, en, rst, we, do);

 input [10:0]   addr;
 input [31:0]   di;
 input          clk, en, rst, we;

 output [31:0]  do;

 parameter	ramDelay = 18;
 parameter	RAM_depth = 2048;
 parameter 	addr_width = 11;
 parameter	RAM_width = 32;

 wire [addr_width-1:0] 	addr;
 wire [RAM_width-1:0] 	di;
 wire clk, en, rst, we;
 wire write0, write1, write2, write3, write4, write5, write6, write7;

 wire [RAM_width-1:0]	do;
 wire [RAM_width-1:0]	do0;
 wire [RAM_width-1:0]	do1;
 wire [RAM_width-1:0]	do2;
 wire [RAM_width-1:0]	do3;
 wire [RAM_width-1:0]	do4;
 wire [RAM_width-1:0]	do5;
 wire [RAM_width-1:0]	do6;
 wire [RAM_width-1:0]	do7;

 reg [31:0] memoryLines [0:31];
 reg tempcount;


 assign write0 = ((en == 1) && (we == 1)&& (addr[10:8]==0))? 1:0;
 assign write1 = ((en == 1) && (we == 1)&& (addr[10:8]==1))? 1:0;
 assign write2 = ((en == 1) && (we == 1)&& (addr[10:8]==2))? 1:0;
 assign write3 = ((en == 1) && (we == 1)&& (addr[10:8]==3))? 1:0;
 assign write4 = ((en == 1) && (we == 1)&& (addr[10:8]==4))? 1:0;
 assign write5 = ((en == 1) && (we == 1)&& (addr[10:8]==5))? 1:0;
 assign write6 = ((en == 1) && (we == 1)&& (addr[10:8]==6))? 1:0;
 assign write7 = ((en == 1) && (we == 1)&& (addr[10:8]==7))? 1:0;

 assign do = (addr[10:8] == 0) ? do0 :
	     (addr[10:8] == 1) ? do1 :
	     (addr[10:8] == 2) ? do2 :
             (addr[10:8] == 3) ? do3 :
	     (addr[10:8] == 4) ? do4 :
	     (addr[10:8] == 5) ? do5 :
	     (addr[10:8] == 6) ? do6 :
	     (addr[10:8] == 7) ? do7 : 0;


 // Our SRAM modules are only 16 bits wide so we have to wire two together


 RAMB4_S16 memBlock0h(.WE(write0),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do0[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[0][0]"
      INIT_01 "$memarrayhigh[0][1]"
      INIT_02 "$memarrayhigh[0][2]"
      INIT_03 "$memarrayhigh[0][3]"
      INIT_04 "$memarrayhigh[0][4]"
      INIT_05 "$memarrayhigh[0][5]"
      INIT_06 "$memarrayhigh[0][6]"
      INIT_07 "$memarrayhigh[0][7]"
      INIT_08 "$memarrayhigh[0][8]"
      INIT_09 "$memarrayhigh[0][9]"
      INIT_0A "$memarrayhigh[0][10]"
      INIT_0B "$memarrayhigh[0][11]"
      INIT_0C "$memarrayhigh[0][12]"
      INIT_0D "$memarrayhigh[0][13]"
      INIT_0E "$memarrayhigh[0][14]"
      INIT_0F "$memarrayhigh[0][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock0h is "$memarrayhigh[0][0]"
   // synthesis attribute INIT_01 of memBlock0h is "$memarrayhigh[0][1]"
   // synthesis attribute INIT_02 of memBlock0h is "$memarrayhigh[0][2]"
   // synthesis attribute INIT_03 of memBlock0h is "$memarrayhigh[0][3]"
   // synthesis attribute INIT_04 of memBlock0h is "$memarrayhigh[0][4]"
   // synthesis attribute INIT_05 of memBlock0h is "$memarrayhigh[0][5]"
   // synthesis attribute INIT_06 of memBlock0h is "$memarrayhigh[0][6]"
   // synthesis attribute INIT_07 of memBlock0h is "$memarrayhigh[0][7]"
   // synthesis attribute INIT_08 of memBlock0h is "$memarrayhigh[0][8]"
   // synthesis attribute INIT_09 of memBlock0h is "$memarrayhigh[0][9]"
   // synthesis attribute INIT_0A of memBlock0h is "$memarrayhigh[0][10]"
   // synthesis attribute INIT_0B of memBlock0h is "$memarrayhigh[0][11]"
   // synthesis attribute INIT_0C of memBlock0h is "$memarrayhigh[0][12]"
   // synthesis attribute INIT_0D of memBlock0h is "$memarrayhigh[0][13]"
   // synthesis attribute INIT_0E of memBlock0h is "$memarrayhigh[0][14]"
   // synthesis attribute INIT_0F of memBlock0h is "$memarrayhigh[0][15]"
   // synopsys translate_off
      defparam memBlock0h.INIT_00 = 256'h$memarrayhigh[0][0];
      defparam memBlock0h.INIT_01 = 256'h$memarrayhigh[0][1];
      defparam memBlock0h.INIT_02 = 256'h$memarrayhigh[0][2];
      defparam memBlock0h.INIT_03 = 256'h$memarrayhigh[0][3];
      defparam memBlock0h.INIT_04 = 256'h$memarrayhigh[0][4];
      defparam memBlock0h.INIT_05 = 256'h$memarrayhigh[0][5];
      defparam memBlock0h.INIT_06 = 256'h$memarrayhigh[0][6];
      defparam memBlock0h.INIT_07 = 256'h$memarrayhigh[0][7];
      defparam memBlock0h.INIT_08 = 256'h$memarrayhigh[0][8];
      defparam memBlock0h.INIT_09 = 256'h$memarrayhigh[0][9];
      defparam memBlock0h.INIT_0A = 256'h$memarrayhigh[0][10];
      defparam memBlock0h.INIT_0B = 256'h$memarrayhigh[0][11];
      defparam memBlock0h.INIT_0C = 256'h$memarrayhigh[0][12];
      defparam memBlock0h.INIT_0D = 256'h$memarrayhigh[0][13];
      defparam memBlock0h.INIT_0E = 256'h$memarrayhigh[0][14];
      defparam memBlock0h.INIT_0F = 256'h$memarrayhigh[0][15];
    // synopsys translate_on

RAMB4_S16 memBlock0l(.WE(write0),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do0[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[0][0]"
      INIT_01 "$memarraylow[0][1]"
      INIT_02 "$memarraylow[0][2]"
      INIT_03 "$memarraylow[0][3]"
      INIT_04 "$memarraylow[0][4]"
      INIT_05 "$memarraylow[0][5]"
      INIT_06 "$memarraylow[0][6]"
      INIT_07 "$memarraylow[0][7]"
      INIT_08 "$memarraylow[0][8]"
      INIT_09 "$memarraylow[0][9]"
      INIT_0A "$memarraylow[0][10]"
      INIT_0B "$memarraylow[0][11]"
      INIT_0C "$memarraylow[0][12]"
      INIT_0D "$memarraylow[0][13]"
      INIT_0E "$memarraylow[0][14]"
      INIT_0F "$memarraylow[0][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock0l is "$memarraylow[0][0]"
   // synthesis attribute INIT_01 of memBlock0l is "$memarraylow[0][1]"
   // synthesis attribute INIT_02 of memBlock0l is "$memarraylow[0][2]"
   // synthesis attribute INIT_03 of memBlock0l is "$memarraylow[0][3]"
   // synthesis attribute INIT_04 of memBlock0l is "$memarraylow[0][4]"
   // synthesis attribute INIT_05 of memBlock0l is "$memarraylow[0][5]"
   // synthesis attribute INIT_06 of memBlock0l is "$memarraylow[0][6]"
   // synthesis attribute INIT_07 of memBlock0l is "$memarraylow[0][7]"
   // synthesis attribute INIT_08 of memBlock0l is "$memarraylow[0][8]"
   // synthesis attribute INIT_09 of memBlock0l is "$memarraylow[0][9]"
   // synthesis attribute INIT_0A of memBlock0l is "$memarraylow[0][10]"
   // synthesis attribute INIT_0B of memBlock0l is "$memarraylow[0][11]"
   // synthesis attribute INIT_0C of memBlock0l is "$memarraylow[0][12]"
   // synthesis attribute INIT_0D of memBlock0l is "$memarraylow[0][13]"
   // synthesis attribute INIT_0E of memBlock0l is "$memarraylow[0][14]"
   // synthesis attribute INIT_0F of memBlock0l is "$memarraylow[0][15]"
   // synopsys translate_off
      defparam memBlock0l.INIT_00 = 256'h$memarraylow[0][0];
      defparam memBlock0l.INIT_01 = 256'h$memarraylow[0][1];
      defparam memBlock0l.INIT_02 = 256'h$memarraylow[0][2];
      defparam memBlock0l.INIT_03 = 256'h$memarraylow[0][3];
      defparam memBlock0l.INIT_04 = 256'h$memarraylow[0][4];
      defparam memBlock0l.INIT_05 = 256'h$memarraylow[0][5];
      defparam memBlock0l.INIT_06 = 256'h$memarraylow[0][6];
      defparam memBlock0l.INIT_07 = 256'h$memarraylow[0][7];
      defparam memBlock0l.INIT_08 = 256'h$memarraylow[0][8];
      defparam memBlock0l.INIT_09 = 256'h$memarraylow[0][9];
      defparam memBlock0l.INIT_0A = 256'h$memarraylow[0][10];
      defparam memBlock0l.INIT_0B = 256'h$memarraylow[0][11];
      defparam memBlock0l.INIT_0C = 256'h$memarraylow[0][12];
      defparam memBlock0l.INIT_0D = 256'h$memarraylow[0][13];
      defparam memBlock0l.INIT_0E = 256'h$memarraylow[0][14];
      defparam memBlock0l.INIT_0F = 256'h$memarraylow[0][15];
    // synopsys translate_on


RAMB4_S16 memBlock1h(.WE(write1),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do1[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[1][0]"
      INIT_01 "$memarrayhigh[1][1]"
      INIT_02 "$memarrayhigh[1][2]"
      INIT_03 "$memarrayhigh[1][3]"
      INIT_04 "$memarrayhigh[1][4]"
      INIT_05 "$memarrayhigh[1][5]"
      INIT_06 "$memarrayhigh[1][6]"
      INIT_07 "$memarrayhigh[1][7]"
      INIT_08 "$memarrayhigh[1][8]"
      INIT_09 "$memarrayhigh[1][9]"
      INIT_0A "$memarrayhigh[1][10]"
      INIT_0B "$memarrayhigh[1][11]"
      INIT_0C "$memarrayhigh[1][12]"
      INIT_0D "$memarrayhigh[1][13]"
      INIT_0E "$memarrayhigh[1][14]"
      INIT_0F "$memarrayhigh[1][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock1h is "$memarrayhigh[1][0]"
   // synthesis attribute INIT_01 of memBlock1h is "$memarrayhigh[1][1]"
   // synthesis attribute INIT_02 of memBlock1h is "$memarrayhigh[1][2]"
   // synthesis attribute INIT_03 of memBlock1h is "$memarrayhigh[1][3]"
   // synthesis attribute INIT_04 of memBlock1h is "$memarrayhigh[1][4]"
   // synthesis attribute INIT_05 of memBlock1h is "$memarrayhigh[1][5]"
   // synthesis attribute INIT_06 of memBlock1h is "$memarrayhigh[1][6]"
   // synthesis attribute INIT_07 of memBlock1h is "$memarrayhigh[1][7]"
   // synthesis attribute INIT_08 of memBlock1h is "$memarrayhigh[1][8]"
   // synthesis attribute INIT_09 of memBlock1h is "$memarrayhigh[1][9]"
   // synthesis attribute INIT_0A of memBlock1h is "$memarrayhigh[1][10]"
   // synthesis attribute INIT_0B of memBlock1h is "$memarrayhigh[1][11]"
   // synthesis attribute INIT_0C of memBlock1h is "$memarrayhigh[1][12]"
   // synthesis attribute INIT_0D of memBlock1h is "$memarrayhigh[1][13]"
   // synthesis attribute INIT_0E of memBlock1h is "$memarrayhigh[1][14]"
   // synthesis attribute INIT_0F of memBlock1h is "$memarrayhigh[1][15]"
   // synopsys translate_off
      defparam memBlock1h.INIT_00 = 256'h$memarrayhigh[1][0];
      defparam memBlock1h.INIT_01 = 256'h$memarrayhigh[1][1];
      defparam memBlock1h.INIT_02 = 256'h$memarrayhigh[1][2];
      defparam memBlock1h.INIT_03 = 256'h$memarrayhigh[1][3];
      defparam memBlock1h.INIT_04 = 256'h$memarrayhigh[1][4];
      defparam memBlock1h.INIT_05 = 256'h$memarrayhigh[1][5];
      defparam memBlock1h.INIT_06 = 256'h$memarrayhigh[1][6];
      defparam memBlock1h.INIT_07 = 256'h$memarrayhigh[1][7];
      defparam memBlock1h.INIT_08 = 256'h$memarrayhigh[1][8];
      defparam memBlock1h.INIT_09 = 256'h$memarrayhigh[1][9];
      defparam memBlock1h.INIT_0A = 256'h$memarrayhigh[1][10];
      defparam memBlock1h.INIT_0B = 256'h$memarrayhigh[1][11];
      defparam memBlock1h.INIT_0C = 256'h$memarrayhigh[1][12];
      defparam memBlock1h.INIT_0D = 256'h$memarrayhigh[1][13];
      defparam memBlock1h.INIT_0E = 256'h$memarrayhigh[1][14];
      defparam memBlock1h.INIT_0F = 256'h$memarrayhigh[1][15];
    // synopsys translate_on


RAMB4_S16 memBlock1l(.WE(write1),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do1[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[1][0]"
      INIT_01 "$memarraylow[1][1]"
      INIT_02 "$memarraylow[1][2]"
      INIT_03 "$memarraylow[1][3]"
      INIT_04 "$memarraylow[1][4]"
      INIT_05 "$memarraylow[1][5]"
      INIT_06 "$memarraylow[1][6]"
      INIT_07 "$memarraylow[1][7]"
      INIT_08 "$memarraylow[1][8]"
      INIT_09 "$memarraylow[1][9]"
      INIT_0A "$memarraylow[1][10]"
      INIT_0B "$memarraylow[1][11]"
      INIT_0C "$memarraylow[1][12]"
      INIT_0D "$memarraylow[1][13]"
      INIT_0E "$memarraylow[1][14]"
      INIT_0F "$memarraylow[1][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock1l is "$memarraylow[1][0]"
   // synthesis attribute INIT_01 of memBlock1l is "$memarraylow[1][1]"
   // synthesis attribute INIT_02 of memBlock1l is "$memarraylow[1][2]"
   // synthesis attribute INIT_03 of memBlock1l is "$memarraylow[1][3]"
   // synthesis attribute INIT_04 of memBlock1l is "$memarraylow[1][4]"
   // synthesis attribute INIT_05 of memBlock1l is "$memarraylow[1][5]"
   // synthesis attribute INIT_06 of memBlock1l is "$memarraylow[1][6]"
   // synthesis attribute INIT_07 of memBlock1l is "$memarraylow[1][7]"
   // synthesis attribute INIT_08 of memBlock1l is "$memarraylow[1][8]"
   // synthesis attribute INIT_09 of memBlock1l is "$memarraylow[1][9]"
   // synthesis attribute INIT_0A of memBlock1l is "$memarraylow[1][10]"
   // synthesis attribute INIT_0B of memBlock1l is "$memarraylow[1][11]"
   // synthesis attribute INIT_0C of memBlock1l is "$memarraylow[1][12]"
   // synthesis attribute INIT_0D of memBlock1l is "$memarraylow[1][13]"
   // synthesis attribute INIT_0E of memBlock1l is "$memarraylow[1][14]"
   // synthesis attribute INIT_0F of memBlock1l is "$memarraylow[1][15]"
   // synopsys translate_off
      defparam memBlock1l.INIT_00 = 256'h$memarraylow[1][0];
      defparam memBlock1l.INIT_01 = 256'h$memarraylow[1][1];
      defparam memBlock1l.INIT_02 = 256'h$memarraylow[1][2];
      defparam memBlock1l.INIT_03 = 256'h$memarraylow[1][3];
      defparam memBlock1l.INIT_04 = 256'h$memarraylow[1][4];
      defparam memBlock1l.INIT_05 = 256'h$memarraylow[1][5];
      defparam memBlock1l.INIT_06 = 256'h$memarraylow[1][6];
      defparam memBlock1l.INIT_07 = 256'h$memarraylow[1][7];
      defparam memBlock1l.INIT_08 = 256'h$memarraylow[1][8];
      defparam memBlock1l.INIT_09 = 256'h$memarraylow[1][9];
      defparam memBlock1l.INIT_0A = 256'h$memarraylow[1][10];
      defparam memBlock1l.INIT_0B = 256'h$memarraylow[1][11];
      defparam memBlock1l.INIT_0C = 256'h$memarraylow[1][12];
      defparam memBlock1l.INIT_0D = 256'h$memarraylow[1][13];
      defparam memBlock1l.INIT_0E = 256'h$memarraylow[1][14];
      defparam memBlock1l.INIT_0F = 256'h$memarraylow[1][15];
    // synopsys translate_on





RAMB4_S16 memBlock2h(.WE(write2),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do2[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[2][0]"
      INIT_01 "$memarrayhigh[2][1]"
      INIT_02 "$memarrayhigh[2][2]"
      INIT_03 "$memarrayhigh[2][3]"
      INIT_04 "$memarrayhigh[2][4]"
      INIT_05 "$memarrayhigh[2][5]"
      INIT_06 "$memarrayhigh[2][6]"
      INIT_07 "$memarrayhigh[2][7]"
      INIT_08 "$memarrayhigh[2][8]"
      INIT_09 "$memarrayhigh[2][9]"
      INIT_0A "$memarrayhigh[2][10]"
      INIT_0B "$memarrayhigh[2][11]"
      INIT_0C "$memarrayhigh[2][12]"
      INIT_0D "$memarrayhigh[2][13]"
      INIT_0E "$memarrayhigh[2][14]"
      INIT_0F "$memarrayhigh[2][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock2h is "$memarrayhigh[2][0]"
   // synthesis attribute INIT_01 of memBlock2h is "$memarrayhigh[2][1]"
   // synthesis attribute INIT_02 of memBlock2h is "$memarrayhigh[2][2]"
   // synthesis attribute INIT_03 of memBlock2h is "$memarrayhigh[2][3]"
   // synthesis attribute INIT_04 of memBlock2h is "$memarrayhigh[2][4]"
   // synthesis attribute INIT_05 of memBlock2h is "$memarrayhigh[2][5]"
   // synthesis attribute INIT_06 of memBlock2h is "$memarrayhigh[2][6]"
   // synthesis attribute INIT_07 of memBlock2h is "$memarrayhigh[2][7]"
   // synthesis attribute INIT_08 of memBlock2h is "$memarrayhigh[2][8]"
   // synthesis attribute INIT_09 of memBlock2h is "$memarrayhigh[2][9]"
   // synthesis attribute INIT_0A of memBlock2h is "$memarrayhigh[2][10]"
   // synthesis attribute INIT_0B of memBlock2h is "$memarrayhigh[2][11]"
   // synthesis attribute INIT_0C of memBlock2h is "$memarrayhigh[2][12]"
   // synthesis attribute INIT_0D of memBlock2h is "$memarrayhigh[2][13]"
   // synthesis attribute INIT_0E of memBlock2h is "$memarrayhigh[2][14]"
   // synthesis attribute INIT_0F of memBlock2h is "$memarrayhigh[2][15]"
   // synopsys translate_off
      defparam memBlock2h.INIT_00 = 256'h$memarrayhigh[2][0];
      defparam memBlock2h.INIT_01 = 256'h$memarrayhigh[2][1];
      defparam memBlock2h.INIT_02 = 256'h$memarrayhigh[2][2];
      defparam memBlock2h.INIT_03 = 256'h$memarrayhigh[2][3];
      defparam memBlock2h.INIT_04 = 256'h$memarrayhigh[2][4];
      defparam memBlock2h.INIT_05 = 256'h$memarrayhigh[2][5];
      defparam memBlock2h.INIT_06 = 256'h$memarrayhigh[2][6];
      defparam memBlock2h.INIT_07 = 256'h$memarrayhigh[2][7];
      defparam memBlock2h.INIT_08 = 256'h$memarrayhigh[2][8];
      defparam memBlock2h.INIT_09 = 256'h$memarrayhigh[2][9];
      defparam memBlock2h.INIT_0A = 256'h$memarrayhigh[2][10];
      defparam memBlock2h.INIT_0B = 256'h$memarrayhigh[2][11];
      defparam memBlock2h.INIT_0C = 256'h$memarrayhigh[2][12];
      defparam memBlock2h.INIT_0D = 256'h$memarrayhigh[2][13];
      defparam memBlock2h.INIT_0E = 256'h$memarrayhigh[2][14];
      defparam memBlock2h.INIT_0F = 256'h$memarrayhigh[2][15];
    // synopsys translate_on


RAMB4_S16 memBlock2l(.WE(write2),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do2[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[2][0]"
      INIT_01 "$memarraylow[2][1]"
      INIT_02 "$memarraylow[2][2]"
      INIT_03 "$memarraylow[2][3]"
      INIT_04 "$memarraylow[2][4]"
      INIT_05 "$memarraylow[2][5]"
      INIT_06 "$memarraylow[2][6]"
      INIT_07 "$memarraylow[2][7]"
      INIT_08 "$memarraylow[2][8]"
      INIT_09 "$memarraylow[2][9]"
      INIT_0A "$memarraylow[2][10]"
      INIT_0B "$memarraylow[2][11]"
      INIT_0C "$memarraylow[2][12]"
      INIT_0D "$memarraylow[2][13]"
      INIT_0E "$memarraylow[2][14]"
      INIT_0F "$memarraylow[2][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock2l is "$memarraylow[2][0]"
   // synthesis attribute INIT_01 of memBlock2l is "$memarraylow[2][1]"
   // synthesis attribute INIT_02 of memBlock2l is "$memarraylow[2][2]"
   // synthesis attribute INIT_03 of memBlock2l is "$memarraylow[2][3]"
   // synthesis attribute INIT_04 of memBlock2l is "$memarraylow[2][4]"
   // synthesis attribute INIT_05 of memBlock2l is "$memarraylow[2][5]"
   // synthesis attribute INIT_06 of memBlock2l is "$memarraylow[2][6]"
   // synthesis attribute INIT_07 of memBlock2l is "$memarraylow[2][7]"
   // synthesis attribute INIT_08 of memBlock2l is "$memarraylow[2][8]"
   // synthesis attribute INIT_09 of memBlock2l is "$memarraylow[2][9]"
   // synthesis attribute INIT_0A of memBlock2l is "$memarraylow[2][10]"
   // synthesis attribute INIT_0B of memBlock2l is "$memarraylow[2][11]"
   // synthesis attribute INIT_0C of memBlock2l is "$memarraylow[2][12]"
   // synthesis attribute INIT_0D of memBlock2l is "$memarraylow[2][13]"
   // synthesis attribute INIT_0E of memBlock2l is "$memarraylow[2][14]"
   // synthesis attribute INIT_0F of memBlock2l is "$memarraylow[2][15]"
   // synopsys translate_off
      defparam memBlock2l.INIT_00 = 256'h$memarraylow[2][0];
      defparam memBlock2l.INIT_01 = 256'h$memarraylow[2][1];
      defparam memBlock2l.INIT_02 = 256'h$memarraylow[2][2];
      defparam memBlock2l.INIT_03 = 256'h$memarraylow[2][3];
      defparam memBlock2l.INIT_04 = 256'h$memarraylow[2][4];
      defparam memBlock2l.INIT_05 = 256'h$memarraylow[2][5];
      defparam memBlock2l.INIT_06 = 256'h$memarraylow[2][6];
      defparam memBlock2l.INIT_07 = 256'h$memarraylow[2][7];
      defparam memBlock2l.INIT_08 = 256'h$memarraylow[2][8];
      defparam memBlock2l.INIT_09 = 256'h$memarraylow[2][9];
      defparam memBlock2l.INIT_0A = 256'h$memarraylow[2][10];
      defparam memBlock2l.INIT_0B = 256'h$memarraylow[2][11];
      defparam memBlock2l.INIT_0C = 256'h$memarraylow[2][12];
      defparam memBlock2l.INIT_0D = 256'h$memarraylow[2][13];
      defparam memBlock2l.INIT_0E = 256'h$memarraylow[2][14];
      defparam memBlock2l.INIT_0F = 256'h$memarraylow[2][15];
    // synopsys translate_on




RAMB4_S16 memBlock3h(.WE(write3),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do3[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[3][0]"
      INIT_01 "$memarrayhigh[3][1]"
      INIT_02 "$memarrayhigh[3][2]"
      INIT_03 "$memarrayhigh[3][3]"
      INIT_04 "$memarrayhigh[3][4]"
      INIT_05 "$memarrayhigh[3][5]"
      INIT_06 "$memarrayhigh[3][6]"
      INIT_07 "$memarrayhigh[3][7]"
      INIT_08 "$memarrayhigh[3][8]"
      INIT_09 "$memarrayhigh[3][9]"
      INIT_0A "$memarrayhigh[3][10]"
      INIT_0B "$memarrayhigh[3][11]"
      INIT_0C "$memarrayhigh[3][12]"
      INIT_0D "$memarrayhigh[3][13]"
      INIT_0E "$memarrayhigh[3][14]"
      INIT_0F "$memarrayhigh[3][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock3h is "$memarrayhigh[3][0]"
   // synthesis attribute INIT_01 of memBlock3h is "$memarrayhigh[3][1]"
   // synthesis attribute INIT_02 of memBlock3h is "$memarrayhigh[3][2]"
   // synthesis attribute INIT_03 of memBlock3h is "$memarrayhigh[3][3]"
   // synthesis attribute INIT_04 of memBlock3h is "$memarrayhigh[3][4]"
   // synthesis attribute INIT_05 of memBlock3h is "$memarrayhigh[3][5]"
   // synthesis attribute INIT_06 of memBlock3h is "$memarrayhigh[3][6]"
   // synthesis attribute INIT_07 of memBlock3h is "$memarrayhigh[3][7]"
   // synthesis attribute INIT_08 of memBlock3h is "$memarrayhigh[3][8]"
   // synthesis attribute INIT_09 of memBlock3h is "$memarrayhigh[3][9]"
   // synthesis attribute INIT_0A of memBlock3h is "$memarrayhigh[3][10]"
   // synthesis attribute INIT_0B of memBlock3h is "$memarrayhigh[3][11]"
   // synthesis attribute INIT_0C of memBlock3h is "$memarrayhigh[3][12]"
   // synthesis attribute INIT_0D of memBlock3h is "$memarrayhigh[3][13]"
   // synthesis attribute INIT_0E of memBlock3h is "$memarrayhigh[3][14]"
   // synthesis attribute INIT_0F of memBlock3h is "$memarrayhigh[3][15]"
   // synopsys translate_off
      defparam memBlock3h.INIT_00 = 256'h$memarrayhigh[3][0];
      defparam memBlock3h.INIT_01 = 256'h$memarrayhigh[3][1];
      defparam memBlock3h.INIT_02 = 256'h$memarrayhigh[3][2];
      defparam memBlock3h.INIT_03 = 256'h$memarrayhigh[3][3];
      defparam memBlock3h.INIT_04 = 256'h$memarrayhigh[3][4];
      defparam memBlock3h.INIT_05 = 256'h$memarrayhigh[3][5];
      defparam memBlock3h.INIT_06 = 256'h$memarrayhigh[3][6];
      defparam memBlock3h.INIT_07 = 256'h$memarrayhigh[3][7];
      defparam memBlock3h.INIT_08 = 256'h$memarrayhigh[3][8];
      defparam memBlock3h.INIT_09 = 256'h$memarrayhigh[3][9];
      defparam memBlock3h.INIT_0A = 256'h$memarrayhigh[3][10];
      defparam memBlock3h.INIT_0B = 256'h$memarrayhigh[3][11];
      defparam memBlock3h.INIT_0C = 256'h$memarrayhigh[3][12];
      defparam memBlock3h.INIT_0D = 256'h$memarrayhigh[3][13];
      defparam memBlock3h.INIT_0E = 256'h$memarrayhigh[3][14];
      defparam memBlock3h.INIT_0F = 256'h$memarrayhigh[3][15];
    // synopsys translate_on

RAMB4_S16 memBlock3l(.WE(write3),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do3[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[3][0]"
      INIT_01 "$memarraylow[3][1]"
      INIT_02 "$memarraylow[3][2]"
      INIT_03 "$memarraylow[3][3]"
      INIT_04 "$memarraylow[3][4]"
      INIT_05 "$memarraylow[3][5]"
      INIT_06 "$memarraylow[3][6]"
      INIT_07 "$memarraylow[3][7]"
      INIT_08 "$memarraylow[3][8]"
      INIT_09 "$memarraylow[3][9]"
      INIT_0A "$memarraylow[3][10]"
      INIT_0B "$memarraylow[3][11]"
      INIT_0C "$memarraylow[3][12]"
      INIT_0D "$memarraylow[3][13]"
      INIT_0E "$memarraylow[3][14]"
      INIT_0F "$memarraylow[3][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock3l is "$memarraylow[3][0]"
   // synthesis attribute INIT_01 of memBlock3l is "$memarraylow[3][1]"
   // synthesis attribute INIT_02 of memBlock3l is "$memarraylow[3][2]"
   // synthesis attribute INIT_03 of memBlock3l is "$memarraylow[3][3]"
   // synthesis attribute INIT_04 of memBlock3l is "$memarraylow[3][4]"
   // synthesis attribute INIT_05 of memBlock3l is "$memarraylow[3][5]"
   // synthesis attribute INIT_06 of memBlock3l is "$memarraylow[3][6]"
   // synthesis attribute INIT_07 of memBlock3l is "$memarraylow[3][7]"
   // synthesis attribute INIT_08 of memBlock3l is "$memarraylow[3][8]"
   // synthesis attribute INIT_09 of memBlock3l is "$memarraylow[3][9]"
   // synthesis attribute INIT_0A of memBlock3l is "$memarraylow[3][10]"
   // synthesis attribute INIT_0B of memBlock3l is "$memarraylow[3][11]"
   // synthesis attribute INIT_0C of memBlock3l is "$memarraylow[3][12]"
   // synthesis attribute INIT_0D of memBlock3l is "$memarraylow[3][13]"
   // synthesis attribute INIT_0E of memBlock3l is "$memarraylow[3][14]"
   // synthesis attribute INIT_0F of memBlock3l is "$memarraylow[3][15]"
   // synopsys translate_off
      defparam memBlock3l.INIT_00 = 256'h$memarraylow[3][0];
      defparam memBlock3l.INIT_01 = 256'h$memarraylow[3][1];
      defparam memBlock3l.INIT_02 = 256'h$memarraylow[3][2];
      defparam memBlock3l.INIT_03 = 256'h$memarraylow[3][3];
      defparam memBlock3l.INIT_04 = 256'h$memarraylow[3][4];
      defparam memBlock3l.INIT_05 = 256'h$memarraylow[3][5];
      defparam memBlock3l.INIT_06 = 256'h$memarraylow[3][6];
      defparam memBlock3l.INIT_07 = 256'h$memarraylow[3][7];
      defparam memBlock3l.INIT_08 = 256'h$memarraylow[3][8];
      defparam memBlock3l.INIT_09 = 256'h$memarraylow[3][9];
      defparam memBlock3l.INIT_0A = 256'h$memarraylow[3][10];
      defparam memBlock3l.INIT_0B = 256'h$memarraylow[3][11];
      defparam memBlock3l.INIT_0C = 256'h$memarraylow[3][12];
      defparam memBlock3l.INIT_0D = 256'h$memarraylow[3][13];
      defparam memBlock3l.INIT_0E = 256'h$memarraylow[3][14];
      defparam memBlock3l.INIT_0F = 256'h$memarraylow[3][15];
    // synopsys translate_on


RAMB4_S16 memBlock4h(.WE(write4),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do4[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[4][0]"
      INIT_01 "$memarrayhigh[4][1]"
      INIT_02 "$memarrayhigh[4][2]"
      INIT_03 "$memarrayhigh[4][3]"
      INIT_04 "$memarrayhigh[4][4]"
      INIT_05 "$memarrayhigh[4][5]"
      INIT_06 "$memarrayhigh[4][6]"
      INIT_07 "$memarrayhigh[4][7]"
      INIT_08 "$memarrayhigh[4][8]"
      INIT_09 "$memarrayhigh[4][9]"
      INIT_0A "$memarrayhigh[4][10]"
      INIT_0B "$memarrayhigh[4][11]"
      INIT_0C "$memarrayhigh[4][12]"
      INIT_0D "$memarrayhigh[4][13]"
      INIT_0E "$memarrayhigh[4][14]"
      INIT_0F "$memarrayhigh[4][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock4h is "$memarrayhigh[4][0]"
   // synthesis attribute INIT_01 of memBlock4h is "$memarrayhigh[4][1]"
   // synthesis attribute INIT_02 of memBlock4h is "$memarrayhigh[4][2]"
   // synthesis attribute INIT_03 of memBlock4h is "$memarrayhigh[4][3]"
   // synthesis attribute INIT_04 of memBlock4h is "$memarrayhigh[4][4]"
   // synthesis attribute INIT_05 of memBlock4h is "$memarrayhigh[4][5]"
   // synthesis attribute INIT_06 of memBlock4h is "$memarrayhigh[4][6]"
   // synthesis attribute INIT_07 of memBlock4h is "$memarrayhigh[4][7]"
   // synthesis attribute INIT_08 of memBlock4h is "$memarrayhigh[4][8]"
   // synthesis attribute INIT_09 of memBlock4h is "$memarrayhigh[4][9]"
   // synthesis attribute INIT_0A of memBlock4h is "$memarrayhigh[4][10]"
   // synthesis attribute INIT_0B of memBlock4h is "$memarrayhigh[4][11]"
   // synthesis attribute INIT_0C of memBlock4h is "$memarrayhigh[4][12]"
   // synthesis attribute INIT_0D of memBlock4h is "$memarrayhigh[4][13]"
   // synthesis attribute INIT_0E of memBlock4h is "$memarrayhigh[4][14]"
   // synthesis attribute INIT_0F of memBlock4h is "$memarrayhigh[4][15]"
   // synopsys translate_off
      defparam memBlock4h.INIT_00 = 256'h$memarrayhigh[4][0];
      defparam memBlock4h.INIT_01 = 256'h$memarrayhigh[4][1];
      defparam memBlock4h.INIT_02 = 256'h$memarrayhigh[4][2];
      defparam memBlock4h.INIT_03 = 256'h$memarrayhigh[4][3];
      defparam memBlock4h.INIT_04 = 256'h$memarrayhigh[4][4];
      defparam memBlock4h.INIT_05 = 256'h$memarrayhigh[4][5];
      defparam memBlock4h.INIT_06 = 256'h$memarrayhigh[4][6];
      defparam memBlock4h.INIT_07 = 256'h$memarrayhigh[4][7];
      defparam memBlock4h.INIT_08 = 256'h$memarrayhigh[4][8];
      defparam memBlock4h.INIT_09 = 256'h$memarrayhigh[4][9];
      defparam memBlock4h.INIT_0A = 256'h$memarrayhigh[4][10];
      defparam memBlock4h.INIT_0B = 256'h$memarrayhigh[4][11];
      defparam memBlock4h.INIT_0C = 256'h$memarrayhigh[4][12];
      defparam memBlock4h.INIT_0D = 256'h$memarrayhigh[4][13];
      defparam memBlock4h.INIT_0E = 256'h$memarrayhigh[4][14];
      defparam memBlock4h.INIT_0F = 256'h$memarrayhigh[4][15];
    // synopsys translate_on

RAMB4_S16 memBlock4l(.WE(write4),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do4[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[4][0]"
      INIT_01 "$memarraylow[4][1]"
      INIT_02 "$memarraylow[4][2]"
      INIT_03 "$memarraylow[4][3]"
      INIT_04 "$memarraylow[4][4]"
      INIT_05 "$memarraylow[4][5]"
      INIT_06 "$memarraylow[4][6]"
      INIT_07 "$memarraylow[4][7]"
      INIT_08 "$memarraylow[4][8]"
      INIT_09 "$memarraylow[4][9]"
      INIT_0A "$memarraylow[4][10]"
      INIT_0B "$memarraylow[4][11]"
      INIT_0C "$memarraylow[4][12]"
      INIT_0D "$memarraylow[4][13]"
      INIT_0E "$memarraylow[4][14]"
      INIT_0F "$memarraylow[4][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock4l is "$memarraylow[4][0]"
   // synthesis attribute INIT_01 of memBlock4l is "$memarraylow[4][1]"
   // synthesis attribute INIT_02 of memBlock4l is "$memarraylow[4][2]"
   // synthesis attribute INIT_03 of memBlock4l is "$memarraylow[4][3]"
   // synthesis attribute INIT_04 of memBlock4l is "$memarraylow[4][4]"
   // synthesis attribute INIT_05 of memBlock4l is "$memarraylow[4][5]"
   // synthesis attribute INIT_06 of memBlock4l is "$memarraylow[4][6]"
   // synthesis attribute INIT_07 of memBlock4l is "$memarraylow[4][7]"
   // synthesis attribute INIT_08 of memBlock4l is "$memarraylow[4][8]"
   // synthesis attribute INIT_09 of memBlock4l is "$memarraylow[4][9]"
   // synthesis attribute INIT_0A of memBlock4l is "$memarraylow[4][10]"
   // synthesis attribute INIT_0B of memBlock4l is "$memarraylow[4][11]"
   // synthesis attribute INIT_0C of memBlock4l is "$memarraylow[4][12]"
   // synthesis attribute INIT_0D of memBlock4l is "$memarraylow[4][13]"
   // synthesis attribute INIT_0E of memBlock4l is "$memarraylow[4][14]"
   // synthesis attribute INIT_0F of memBlock4l is "$memarraylow[4][15]"
   // synopsys translate_off
      defparam memBlock4l.INIT_00 = 256'h$memarraylow[4][0];
      defparam memBlock4l.INIT_01 = 256'h$memarraylow[4][1];
      defparam memBlock4l.INIT_02 = 256'h$memarraylow[4][2];
      defparam memBlock4l.INIT_03 = 256'h$memarraylow[4][3];
      defparam memBlock4l.INIT_04 = 256'h$memarraylow[4][4];
      defparam memBlock4l.INIT_05 = 256'h$memarraylow[4][5];
      defparam memBlock4l.INIT_06 = 256'h$memarraylow[4][6];
      defparam memBlock4l.INIT_07 = 256'h$memarraylow[4][7];
      defparam memBlock4l.INIT_08 = 256'h$memarraylow[4][8];
      defparam memBlock4l.INIT_09 = 256'h$memarraylow[4][9];
      defparam memBlock4l.INIT_0A = 256'h$memarraylow[4][10];
      defparam memBlock4l.INIT_0B = 256'h$memarraylow[4][11];
      defparam memBlock4l.INIT_0C = 256'h$memarraylow[4][12];
      defparam memBlock4l.INIT_0D = 256'h$memarraylow[4][13];
      defparam memBlock4l.INIT_0E = 256'h$memarraylow[4][14];
      defparam memBlock4l.INIT_0F = 256'h$memarraylow[4][15];
    // synopsys translate_on


RAMB4_S16 memBlock5h(.WE(write5),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do5[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[5][0]"
      INIT_01 "$memarrayhigh[5][1]"
      INIT_02 "$memarrayhigh[5][2]"
      INIT_03 "$memarrayhigh[5][3]"
      INIT_04 "$memarrayhigh[5][4]"
      INIT_05 "$memarrayhigh[5][5]"
      INIT_06 "$memarrayhigh[5][6]"
      INIT_07 "$memarrayhigh[5][7]"
      INIT_08 "$memarrayhigh[5][8]"
      INIT_09 "$memarrayhigh[5][9]"
      INIT_0A "$memarrayhigh[5][10]"
      INIT_0B "$memarrayhigh[5][11]"
      INIT_0C "$memarrayhigh[5][12]"
      INIT_0D "$memarrayhigh[5][13]"
      INIT_0E "$memarrayhigh[5][14]"
      INIT_0F "$memarrayhigh[5][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock5h is "$memarrayhigh[5][0]"
   // synthesis attribute INIT_01 of memBlock5h is "$memarrayhigh[5][1]"
   // synthesis attribute INIT_02 of memBlock5h is "$memarrayhigh[5][2]"
   // synthesis attribute INIT_03 of memBlock5h is "$memarrayhigh[5][3]"
   // synthesis attribute INIT_04 of memBlock5h is "$memarrayhigh[5][4]"
   // synthesis attribute INIT_05 of memBlock5h is "$memarrayhigh[5][5]"
   // synthesis attribute INIT_06 of memBlock5h is "$memarrayhigh[5][6]"
   // synthesis attribute INIT_07 of memBlock5h is "$memarrayhigh[5][7]"
   // synthesis attribute INIT_08 of memBlock5h is "$memarrayhigh[5][8]"
   // synthesis attribute INIT_09 of memBlock5h is "$memarrayhigh[5][9]"
   // synthesis attribute INIT_0A of memBlock5h is "$memarrayhigh[5][10]"
   // synthesis attribute INIT_0B of memBlock5h is "$memarrayhigh[5][11]"
   // synthesis attribute INIT_0C of memBlock5h is "$memarrayhigh[5][12]"
   // synthesis attribute INIT_0D of memBlock5h is "$memarrayhigh[5][13]"
   // synthesis attribute INIT_0E of memBlock5h is "$memarrayhigh[5][14]"
   // synthesis attribute INIT_0F of memBlock5h is "$memarrayhigh[5][15]"
   // synopsys translate_off
      defparam memBlock5h.INIT_00 = 256'h$memarrayhigh[5][0];
      defparam memBlock5h.INIT_01 = 256'h$memarrayhigh[5][1];
      defparam memBlock5h.INIT_02 = 256'h$memarrayhigh[5][2];
      defparam memBlock5h.INIT_03 = 256'h$memarrayhigh[5][3];
      defparam memBlock5h.INIT_04 = 256'h$memarrayhigh[5][4];
      defparam memBlock5h.INIT_05 = 256'h$memarrayhigh[5][5];
      defparam memBlock5h.INIT_06 = 256'h$memarrayhigh[5][6];
      defparam memBlock5h.INIT_07 = 256'h$memarrayhigh[5][7];
      defparam memBlock5h.INIT_08 = 256'h$memarrayhigh[5][8];
      defparam memBlock5h.INIT_09 = 256'h$memarrayhigh[5][9];
      defparam memBlock5h.INIT_0A = 256'h$memarrayhigh[5][10];
      defparam memBlock5h.INIT_0B = 256'h$memarrayhigh[5][11];
      defparam memBlock5h.INIT_0C = 256'h$memarrayhigh[5][12];
      defparam memBlock5h.INIT_0D = 256'h$memarrayhigh[5][13];
      defparam memBlock5h.INIT_0E = 256'h$memarrayhigh[5][14];
      defparam memBlock5h.INIT_0F = 256'h$memarrayhigh[5][15];
    // synopsys translate_on

RAMB4_S16 memBlock5l(.WE(write5),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do5[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[5][0]"
      INIT_01 "$memarraylow[5][1]"
      INIT_02 "$memarraylow[5][2]"
      INIT_03 "$memarraylow[5][3]"
      INIT_04 "$memarraylow[5][4]"
      INIT_05 "$memarraylow[5][5]"
      INIT_06 "$memarraylow[5][6]"
      INIT_07 "$memarraylow[5][7]"
      INIT_08 "$memarraylow[5][8]"
      INIT_09 "$memarraylow[5][9]"
      INIT_0A "$memarraylow[5][10]"
      INIT_0B "$memarraylow[5][11]"
      INIT_0C "$memarraylow[5][12]"
      INIT_0D "$memarraylow[5][13]"
      INIT_0E "$memarraylow[5][14]"
      INIT_0F "$memarraylow[5][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock5l is "$memarraylow[5][0]"
   // synthesis attribute INIT_01 of memBlock5l is "$memarraylow[5][1]"
   // synthesis attribute INIT_02 of memBlock5l is "$memarraylow[5][2]"
   // synthesis attribute INIT_03 of memBlock5l is "$memarraylow[5][3]"
   // synthesis attribute INIT_04 of memBlock5l is "$memarraylow[5][4]"
   // synthesis attribute INIT_05 of memBlock5l is "$memarraylow[5][5]"
   // synthesis attribute INIT_06 of memBlock5l is "$memarraylow[5][6]"
   // synthesis attribute INIT_07 of memBlock5l is "$memarraylow[5][7]"
   // synthesis attribute INIT_08 of memBlock5l is "$memarraylow[5][8]"
   // synthesis attribute INIT_09 of memBlock5l is "$memarraylow[5][9]"
   // synthesis attribute INIT_0A of memBlock5l is "$memarraylow[5][10]"
   // synthesis attribute INIT_0B of memBlock5l is "$memarraylow[5][11]"
   // synthesis attribute INIT_0C of memBlock5l is "$memarraylow[5][12]"
   // synthesis attribute INIT_0D of memBlock5l is "$memarraylow[5][13]"
   // synthesis attribute INIT_0E of memBlock5l is "$memarraylow[5][14]"
   // synthesis attribute INIT_0F of memBlock5l is "$memarraylow[5][15]"
   // synopsys translate_off
      defparam memBlock5l.INIT_00 = 256'h$memarraylow[5][0];
      defparam memBlock5l.INIT_01 = 256'h$memarraylow[5][1];
      defparam memBlock5l.INIT_02 = 256'h$memarraylow[5][2];
      defparam memBlock5l.INIT_03 = 256'h$memarraylow[5][3];
      defparam memBlock5l.INIT_04 = 256'h$memarraylow[5][4];
      defparam memBlock5l.INIT_05 = 256'h$memarraylow[5][5];
      defparam memBlock5l.INIT_06 = 256'h$memarraylow[5][6];
      defparam memBlock5l.INIT_07 = 256'h$memarraylow[5][7];
      defparam memBlock5l.INIT_08 = 256'h$memarraylow[5][8];
      defparam memBlock5l.INIT_09 = 256'h$memarraylow[5][9];
      defparam memBlock5l.INIT_0A = 256'h$memarraylow[5][10];
      defparam memBlock5l.INIT_0B = 256'h$memarraylow[5][11];
      defparam memBlock5l.INIT_0C = 256'h$memarraylow[5][12];
      defparam memBlock5l.INIT_0D = 256'h$memarraylow[5][13];
      defparam memBlock5l.INIT_0E = 256'h$memarraylow[5][14];
      defparam memBlock5l.INIT_0F = 256'h$memarraylow[5][15];
    // synopsys translate_on


RAMB4_S16 memBlock6h(.WE(write6),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do6[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[6][0]"
      INIT_01 "$memarrayhigh[6][1]"
      INIT_02 "$memarrayhigh[6][2]"
      INIT_03 "$memarrayhigh[6][3]"
      INIT_04 "$memarrayhigh[6][4]"
      INIT_05 "$memarrayhigh[6][5]"
      INIT_06 "$memarrayhigh[6][6]"
      INIT_07 "$memarrayhigh[6][7]"
      INIT_08 "$memarrayhigh[6][8]"
      INIT_09 "$memarrayhigh[6][9]"
      INIT_0A "$memarrayhigh[6][10]"
      INIT_0B "$memarrayhigh[6][11]"
      INIT_0C "$memarrayhigh[6][12]"
      INIT_0D "$memarrayhigh[6][13]"
      INIT_0E "$memarrayhigh[6][14]"
      INIT_0F "$memarrayhigh[6][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock6h is "$memarrayhigh[6][0]"
   // synthesis attribute INIT_01 of memBlock6h is "$memarrayhigh[6][1]"
   // synthesis attribute INIT_02 of memBlock6h is "$memarrayhigh[6][2]"
   // synthesis attribute INIT_03 of memBlock6h is "$memarrayhigh[6][3]"
   // synthesis attribute INIT_04 of memBlock6h is "$memarrayhigh[6][4]"
   // synthesis attribute INIT_05 of memBlock6h is "$memarrayhigh[6][5]"
   // synthesis attribute INIT_06 of memBlock6h is "$memarrayhigh[6][6]"
   // synthesis attribute INIT_07 of memBlock6h is "$memarrayhigh[6][7]"
   // synthesis attribute INIT_08 of memBlock6h is "$memarrayhigh[6][8]"
   // synthesis attribute INIT_09 of memBlock6h is "$memarrayhigh[6][9]"
   // synthesis attribute INIT_0A of memBlock6h is "$memarrayhigh[6][10]"
   // synthesis attribute INIT_0B of memBlock6h is "$memarrayhigh[6][11]"
   // synthesis attribute INIT_0C of memBlock6h is "$memarrayhigh[6][12]"
   // synthesis attribute INIT_0D of memBlock6h is "$memarrayhigh[6][13]"
   // synthesis attribute INIT_0E of memBlock6h is "$memarrayhigh[6][14]"
   // synthesis attribute INIT_0F of memBlock6h is "$memarrayhigh[6][15]"
   // synopsys translate_off
      defparam memBlock6h.INIT_00 = 256'h$memarrayhigh[6][0];
      defparam memBlock6h.INIT_01 = 256'h$memarrayhigh[6][1];
      defparam memBlock6h.INIT_02 = 256'h$memarrayhigh[6][2];
      defparam memBlock6h.INIT_03 = 256'h$memarrayhigh[6][3];
      defparam memBlock6h.INIT_04 = 256'h$memarrayhigh[6][4];
      defparam memBlock6h.INIT_05 = 256'h$memarrayhigh[6][5];
      defparam memBlock6h.INIT_06 = 256'h$memarrayhigh[6][6];
      defparam memBlock6h.INIT_07 = 256'h$memarrayhigh[6][7];
      defparam memBlock6h.INIT_08 = 256'h$memarrayhigh[6][8];
      defparam memBlock6h.INIT_09 = 256'h$memarrayhigh[6][9];
      defparam memBlock6h.INIT_0A = 256'h$memarrayhigh[6][10];
      defparam memBlock6h.INIT_0B = 256'h$memarrayhigh[6][11];
      defparam memBlock6h.INIT_0C = 256'h$memarrayhigh[6][12];
      defparam memBlock6h.INIT_0D = 256'h$memarrayhigh[6][13];
      defparam memBlock6h.INIT_0E = 256'h$memarrayhigh[6][14];
      defparam memBlock6h.INIT_0F = 256'h$memarrayhigh[6][15];
    // synopsys translate_on


RAMB4_S16 memBlock6l(.WE(write6),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do6[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[6][0]"
      INIT_01 "$memarraylow[6][1]"
      INIT_02 "$memarraylow[6][2]"
      INIT_03 "$memarraylow[6][3]"
      INIT_04 "$memarraylow[6][4]"
      INIT_05 "$memarraylow[6][5]"
      INIT_06 "$memarraylow[6][6]"
      INIT_07 "$memarraylow[6][7]"
      INIT_08 "$memarraylow[6][8]"
      INIT_09 "$memarraylow[6][9]"
      INIT_0A "$memarraylow[6][10]"
      INIT_0B "$memarraylow[6][11]"
      INIT_0C "$memarraylow[6][12]"
      INIT_0D "$memarraylow[6][13]"
      INIT_0E "$memarraylow[6][14]"
      INIT_0F "$memarraylow[6][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock6l is "$memarraylow[6][0]"
   // synthesis attribute INIT_01 of memBlock6l is "$memarraylow[6][1]"
   // synthesis attribute INIT_02 of memBlock6l is "$memarraylow[6][2]"
   // synthesis attribute INIT_03 of memBlock6l is "$memarraylow[6][3]"
   // synthesis attribute INIT_04 of memBlock6l is "$memarraylow[6][4]"
   // synthesis attribute INIT_05 of memBlock6l is "$memarraylow[6][5]"
   // synthesis attribute INIT_06 of memBlock6l is "$memarraylow[6][6]"
   // synthesis attribute INIT_07 of memBlock6l is "$memarraylow[6][7]"
   // synthesis attribute INIT_08 of memBlock6l is "$memarraylow[6][8]"
   // synthesis attribute INIT_09 of memBlock6l is "$memarraylow[6][9]"
   // synthesis attribute INIT_0A of memBlock6l is "$memarraylow[6][10]"
   // synthesis attribute INIT_0B of memBlock6l is "$memarraylow[6][11]"
   // synthesis attribute INIT_0C of memBlock6l is "$memarraylow[6][12]"
   // synthesis attribute INIT_0D of memBlock6l is "$memarraylow[6][13]"
   // synthesis attribute INIT_0E of memBlock6l is "$memarraylow[6][14]"
   // synthesis attribute INIT_0F of memBlock6l is "$memarraylow[6][15]"
   // synopsys translate_off
      defparam memBlock6l.INIT_00 = 256'h$memarraylow[6][0];
      defparam memBlock6l.INIT_01 = 256'h$memarraylow[6][1];
      defparam memBlock6l.INIT_02 = 256'h$memarraylow[6][2];
      defparam memBlock6l.INIT_03 = 256'h$memarraylow[6][3];
      defparam memBlock6l.INIT_04 = 256'h$memarraylow[6][4];
      defparam memBlock6l.INIT_05 = 256'h$memarraylow[6][5];
      defparam memBlock6l.INIT_06 = 256'h$memarraylow[6][6];
      defparam memBlock6l.INIT_07 = 256'h$memarraylow[6][7];
      defparam memBlock6l.INIT_08 = 256'h$memarraylow[6][8];
      defparam memBlock6l.INIT_09 = 256'h$memarraylow[6][9];
      defparam memBlock6l.INIT_0A = 256'h$memarraylow[6][10];
      defparam memBlock6l.INIT_0B = 256'h$memarraylow[6][11];
      defparam memBlock6l.INIT_0C = 256'h$memarraylow[6][12];
      defparam memBlock6l.INIT_0D = 256'h$memarraylow[6][13];
      defparam memBlock6l.INIT_0E = 256'h$memarraylow[6][14];
      defparam memBlock6l.INIT_0F = 256'h$memarraylow[6][15];
    // synopsys translate_on


RAMB4_S16 memBlock7h(.WE(write7),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[31:16]),.DO(do7[31:16]));
   /* synopsys attribute
      INIT_00 "$memarrayhigh[7][0]"
      INIT_01 "$memarrayhigh[7][1]"
      INIT_02 "$memarrayhigh[7][2]"
      INIT_03 "$memarrayhigh[7][3]"
      INIT_04 "$memarrayhigh[7][4]"
      INIT_05 "$memarrayhigh[7][5]"
      INIT_06 "$memarrayhigh[7][6]"
      INIT_07 "$memarrayhigh[7][7]"
      INIT_08 "$memarrayhigh[7][8]"
      INIT_09 "$memarrayhigh[7][9]"
      INIT_0A "$memarrayhigh[7][10]"
      INIT_0B "$memarrayhigh[7][11]"
      INIT_0C "$memarrayhigh[7][12]"
      INIT_0D "$memarrayhigh[7][13]"
      INIT_0E "$memarrayhigh[7][14]"
      INIT_0F "$memarrayhigh[7][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock7h is "$memarrayhigh[7][0]"
   // synthesis attribute INIT_01 of memBlock7h is "$memarrayhigh[7][1]"
   // synthesis attribute INIT_02 of memBlock7h is "$memarrayhigh[7][2]"
   // synthesis attribute INIT_03 of memBlock7h is "$memarrayhigh[7][3]"
   // synthesis attribute INIT_04 of memBlock7h is "$memarrayhigh[7][4]"
   // synthesis attribute INIT_05 of memBlock7h is "$memarrayhigh[7][5]"
   // synthesis attribute INIT_06 of memBlock7h is "$memarrayhigh[7][6]"
   // synthesis attribute INIT_07 of memBlock7h is "$memarrayhigh[7][7]"
   // synthesis attribute INIT_08 of memBlock7h is "$memarrayhigh[7][8]"
   // synthesis attribute INIT_09 of memBlock7h is "$memarrayhigh[7][9]"
   // synthesis attribute INIT_0A of memBlock7h is "$memarrayhigh[7][10]"
   // synthesis attribute INIT_0B of memBlock7h is "$memarrayhigh[7][11]"
   // synthesis attribute INIT_0C of memBlock7h is "$memarrayhigh[7][12]"
   // synthesis attribute INIT_0D of memBlock7h is "$memarrayhigh[7][13]"
   // synthesis attribute INIT_0E of memBlock7h is "$memarrayhigh[7][14]"
   // synthesis attribute INIT_0F of memBlock7h is "$memarrayhigh[7][15]"
   // synopsys translate_off
      defparam memBlock7h.INIT_00 = 256'h$memarrayhigh[7][0];
      defparam memBlock7h.INIT_01 = 256'h$memarrayhigh[7][1];
      defparam memBlock7h.INIT_02 = 256'h$memarrayhigh[7][2];
      defparam memBlock7h.INIT_03 = 256'h$memarrayhigh[7][3];
      defparam memBlock7h.INIT_04 = 256'h$memarrayhigh[7][4];
      defparam memBlock7h.INIT_05 = 256'h$memarrayhigh[7][5];
      defparam memBlock7h.INIT_06 = 256'h$memarrayhigh[7][6];
      defparam memBlock7h.INIT_07 = 256'h$memarrayhigh[7][7];
      defparam memBlock7h.INIT_08 = 256'h$memarrayhigh[7][8];
      defparam memBlock7h.INIT_09 = 256'h$memarrayhigh[7][9];
      defparam memBlock7h.INIT_0A = 256'h$memarrayhigh[7][10];
      defparam memBlock7h.INIT_0B = 256'h$memarrayhigh[7][11];
      defparam memBlock7h.INIT_0C = 256'h$memarrayhigh[7][12];
      defparam memBlock7h.INIT_0D = 256'h$memarrayhigh[7][13];
      defparam memBlock7h.INIT_0E = 256'h$memarrayhigh[7][14];
      defparam memBlock7h.INIT_0F = 256'h$memarrayhigh[7][15];
    // synopsys translate_on

RAMB4_S16 memBlock7l(.WE(write7),.EN(en),.RST(rst),.CLK(clk),.ADDR(addr[7:0]),.DI(di[15:0]),.DO(do7[15:0]));
   /* synopsys attribute
      INIT_00 "$memarraylow[7][0]"
      INIT_01 "$memarraylow[7][1]"
      INIT_02 "$memarraylow[7][2]"
      INIT_03 "$memarraylow[7][3]"
      INIT_04 "$memarraylow[7][4]"
      INIT_05 "$memarraylow[7][5]"
      INIT_06 "$memarraylow[7][6]"
      INIT_07 "$memarraylow[7][7]"
      INIT_08 "$memarraylow[7][8]"
      INIT_09 "$memarraylow[7][9]"
      INIT_0A "$memarraylow[7][10]"
      INIT_0B "$memarraylow[7][11]"
      INIT_0C "$memarraylow[7][12]"
      INIT_0D "$memarraylow[7][13]"
      INIT_0E "$memarraylow[7][14]"
      INIT_0F "$memarraylow[7][15]"
      fpga_dont_touch "1"
   */
   // synthesis attribute INIT_00 of memBlock7l is "$memarraylow[7][0]"
   // synthesis attribute INIT_01 of memBlock7l is "$memarraylow[7][1]"
   // synthesis attribute INIT_02 of memBlock7l is "$memarraylow[7][2]"
   // synthesis attribute INIT_03 of memBlock7l is "$memarraylow[7][3]"
   // synthesis attribute INIT_04 of memBlock7l is "$memarraylow[7][4]"
   // synthesis attribute INIT_05 of memBlock7l is "$memarraylow[7][5]"
   // synthesis attribute INIT_06 of memBlock7l is "$memarraylow[7][6]"
   // synthesis attribute INIT_07 of memBlock7l is "$memarraylow[7][7]"
   // synthesis attribute INIT_08 of memBlock7l is "$memarraylow[7][8]"
   // synthesis attribute INIT_09 of memBlock7l is "$memarraylow[7][9]"
   // synthesis attribute INIT_0A of memBlock7l is "$memarraylow[7][10]"
   // synthesis attribute INIT_0B of memBlock7l is "$memarraylow[7][11]"
   // synthesis attribute INIT_0C of memBlock7l is "$memarraylow[7][12]"
   // synthesis attribute INIT_0D of memBlock7l is "$memarraylow[7][13]"
   // synthesis attribute INIT_0E of memBlock7l is "$memarraylow[7][14]"
   // synthesis attribute INIT_0F of memBlock7l is "$memarraylow[7][15]"
   // synopsys translate_off
      defparam memBlock7l.INIT_00 = 256'h$memarraylow[7][0];
      defparam memBlock7l.INIT_01 = 256'h$memarraylow[7][1];
      defparam memBlock7l.INIT_02 = 256'h$memarraylow[7][2];
      defparam memBlock7l.INIT_03 = 256'h$memarraylow[7][3];
      defparam memBlock7l.INIT_04 = 256'h$memarraylow[7][4];
      defparam memBlock7l.INIT_05 = 256'h$memarraylow[7][5];
      defparam memBlock7l.INIT_06 = 256'h$memarraylow[7][6];
      defparam memBlock7l.INIT_07 = 256'h$memarraylow[7][7];
      defparam memBlock7l.INIT_08 = 256'h$memarraylow[7][8];
      defparam memBlock7l.INIT_09 = 256'h$memarraylow[7][9];
      defparam memBlock7l.INIT_0A = 256'h$memarraylow[7][10];
      defparam memBlock7l.INIT_0B = 256'h$memarraylow[7][11];
      defparam memBlock7l.INIT_0C = 256'h$memarraylow[7][12];
      defparam memBlock7l.INIT_0D = 256'h$memarraylow[7][13];
      defparam memBlock7l.INIT_0E = 256'h$memarraylow[7][14];
      defparam memBlock7l.INIT_0F = 256'h$memarraylow[7][15];
    // synopsys translate_on

endmodule


ENDWSS

print OUT $foo;
print $foo if $DEBUG;

}