CS 61C Quiz - Week 4-2-1: Wednesday

Question 1:

How does the C programmer associate the arguments of a function at the
caller with the callee? How is it normally done in Verilog?

Question 2:

Write the Verilog for a system clock called CLK with which
oscillates between 0 and 1 every 2 seconds, that is, a 4 ns oscillation
period.

Question 3:

How many wires will be necessary in a module that implements the following
(unsimplified) Boolean expression?  Briefly explain your answer.
        _       _
 E = AB C + A C B

Assume that the inputs are A, B, and C, the output is E, and each AND and
OR gate has only two inputs.

Question 4:

Your friend says the following Verilog code would cause "undefined
results."

initial
  begin
    s=0; a=0; b=1; expected=0;
    a=1; b=0; expected=1;       // #10 omitte

initial
  $monitor (
    "select=%b in0=%b in1=%b out=%b expected=%b time=%d", 
    s, a, b, f, expected, $time);

Elaborate on what the undefined results might be, and the reasons they
might appear as you describe.

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