CS 61C Quiz - Week 5-2-2: Thursday

Question 1:

What is a branch delay slot? Why function does it serve?

Question 2:

The following sequence of instructions cannot run
at full speed on the pipelined datapath without
special hardware:

lw $to 0($s1)
add $t1 $t0 $t0

Why not? What sort of hardware (or software) schemes
can we use to get reduce the peformance penalty?

Question 3:

Suppose we want to cut down on the transistor count
of our processor by having only 1 memory module
(as opposed to both an instructiona and a data 
memory). Why will this break our pipelining scheme?

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