Answer from cs61c-ej (Leon Wang 16247444) for Question 3
Debugging in Verilog is difficult because you can't step through the code.  I don't mind coding in Verilog if necessary.  Syntax isn't a problem for me.

But for a large open ended project in Verilog, I can see that a lot of planning is necessar.

Structural was pretty easy to learn.  I don't like initials, always, begins, and ends.