Answer from cs61c-av (Kenneth Wong 16192104) for Question 1
I'm not exactly sure by what the question means when it says behave as expected.  But there is a "clk-to-q" delay and a hold time between a flip flop's input to output.  So if they are connected as described above, the 2nd flip flop's input might come in a bit late, every two clock cycles, due to the delays of the first flip flop.  So the output Q at the 2nd flip flop might look like: 00110011...