Answer from cs61c-bx (Tuan Ha 16989532) for Question 1
The circuit may not behave as expected because of flip flops' "clk-to-q" delay. However, if the input data d is stable for a long enough period and the clock is not alternating too fast between 1 and 0, the circuit will behave properly. So, depending on the input and the clock signals, the circuit will behave accordingly.