Answer from cs61c-cb (minh uyen nguyen 16765774) for Question 1
If the wire that connects them has no delay, this circuit will not behave as expected.  Because flip-flops cannot change their outputs instantaneously.  Also, time is needed to transfer inputs internally.  Therefore, the input d must be stable for a short amount of time before the rising edge of the clock and remain stable for a short amount of time after the edge.  It means that if there is no delay, the input of the second flip-flops (which is the output of the first flip=flops) will not have time to stay stable before the rising edge of the clock.

The setup time and the hold time creates a window when the input d cannot change.  If it changes in this window, the flip-flops will not reliably capture the new data input.