Answer from cs61c-cj (Peter Lau 16539384) for Question 1
If two D flip-flops were hooked up end-to-end and the wire that connected them had no delay, the second flip-flop might have some problems capturing the "correct" value from the first flip-flop.  Looking at the first flip-flop, the delay of Q taking on D's value after the rising clock edge is the clk-to-q delay.  This Q is the second flip-flop's D input.  Looking at the second flip-flop, if the first flip-flop's clk-to-q delay was smaller than the necessary hold time for the second flip-flop, it would not capture the correct value from the first flip-flop.