Quiz submission record for quiz4-1-2 at Tue Jul 13 01:00:20 2004:

Your Answer for Question 1:
no the circuit will not behave as expected because flip-flops require a clk-to-q delay to remain constant so that the input data will be transferred into the Q output correctly.  the Q output will change to the the current D input only when then CLK is a positive clock edge.

Your Answer for Question 2:
a graphing calcultor
digital AM/FM tuners 
Television


Your unique submission ID is quiz4-1-2-cs61c-ao-1089705620-1122.