Answer from cs61c-ac (U alias Vitoria Lok 16597715) for Question 1
In C, the arguments(only names in caller function are required) are placed inside parenthesis following the name of the function. The order of the arguments must be the same as the one in the function declaration.

In Verilog, the arguments (both the names in the caller and callee functions are included) are placed in the parenthesis. Using the dot notation, the order of the arguments are not important.