Answer from cs61c-av (Kenneth Wong 16192104) for Question 1
First you need to instantiate the module and give it a local name: “mux2 myMux ...”The local name is used to distinguish from other instances of mux2 that we might make.  After that you have a list of connections.  The syntax used here lists the ports of mux2 in arbitrary order, each one preceded by a “.”, and followed by the name of a local signal in parentheses. Verilog also allows making connections between local signals and module ports by simply listing the names of the local signals in the order that the ports where defined in the module header. However, the “dot” form because it allows you to list the ports in any order, making it easier to make changes later, and provides a reminder of exactly which signal is being connected to what port.