Answer from cs61c-ax (Amanda Alfonso 15906918) for Question 1
In C, the callee is a function method with arbitrary arguments (i.e. int square(int x) where x is an arbitrary int).  The caller calls the callee by passing an argument with which the callee will need to operate (i.e. the caller may call square(5)).  Interestingly, Verilog "sorta" combines these two steps - such as seen in the testbench for mux2.  In Verilog, a module is declared much like C with arbitrary arguments (i.e. module mux2(in0, in1, select, out)) - however, when a module is instantiated and thus calls the module callee, the caller testmux passes the ports and the name of the local signal (i.e. myMux(.select(s)...) where .select is the port and s is the local name).