Answer from cs61c-bd (Dae-hyeon-Wi 17782249) for Question 1
The callee copys the arguments of caller.

Caller{
    Callee(1,2);
}

void Callee(int a , int b){
}

a is 1, b is 2.
 
In Verilog, Caller links each arguments for callee like followings

module caller;
    reg a,b,s
    wire f;
    callee mycallee(.first(s), .second(a), .third(b)  
                    , .fourth(d));
endmodule

..

module callee(first, second, third, fourth);
...
endmodule