Answer from cs61c-cf (Aspandiar Dahmubed 16812056) for Question 1
In C we pass variables by value or by address to a function without the knowledge of who is being called or what called it except that it has received values and at the end of the function, the answer will be returned to the function that called it. 
In Verilog, we normally create instantiations of the function being called and follow with a list of connections between our local signals and the ports of the function being called.