Answer from cs61c-el (David Tung 16479725) for Question 1
Formatwise, it is very similar.  The C programmer just has the arguments in the function call in the same order that they appear in the function definition foo(x, y, z).  Verilog is very similar in that it looks the same, except that arguments to a module in Verilog do not have to be in the same order if their identity is specified; otherwise, it is much the same.  Like module(.in(x), .out(y))