Answer from cs61c-eq (Nicholas Hwang 16732453) for Question 1
C programmers pass arguments as parameters to a function to associate the arguments between caller and callee. But after the data is sent to the callee, it is temporarily out of the caller's hands. In Verilog, there are no functions so to speak, but modules do take arguments like normal functions, except they are manipulated by the caller outside of the called module.