Answer from cs61c-et (Bryant Chae 14937777) for Question 1
THe C programmer assciates the arguements of a function at the caller with the callee by using the function name and the arguements in parenthesis. Verilog does this by having a user-defined module, followed by a list of signals. These signals define the interface of the module to other modules. When a module is instaintianted, these port like things are bound together to other signals for interconnection with other modules.