Answer from cs61c-ev (Roland Carlos 16583196) for Question 1
In C, you would have to match up the arguments in order. So, when you call a function, the arguments you pass in must match up with the arguments in the function, otherwise you'll get wrong type of variable (a type mismatch) or just pass in the wrong variable to be used in the function.

In Verilog, you can make connections between local signals and module ports by listing the ports of the function is arbitrary order, each order preceded by a "." and followed by the name of a local signal in parentheses. The main benefit of this form is that order does not matter which makes changes easier later on.