Answer from cs61c-cb (minh uyen nguyen 16765774) for Question 2
module CLK(IN, OUT);
   input IN;
   output OUT;
   wire state0, state1, currentState;

   if(IN) #1 OUT = 1; else #1 OUT = 0

endmodule //I don't know how to write Verilog for this
          //It's wrong.