Answer from cs61c-et (Bryant Chae 14937777) for Question 2
module CLK()
input D;
input CLK, RST;
output Q;
reg Q;
always @ (posedge CLK)
if (RST) #1 Q = 0; else #1 Q = D;
endmodule 

module parityChecker (OUT, IN, CLK, RST);
output OUT;
input IN;
input CLK, RST;
wire currentState, nextState;
#1 xor (nextState, IN, currentState);
buf (OUT, nextState);
endmodule