Answer from cs61c-aj (Kevin Li 15855812) for Question 4
Since there is no #10 that means that both lines are excuted at the same time. In Verilog, time is counted by # otherwise all lines start at the same time at the beginning. So the results are undefined because at the beginning both lines start excuting the code and a could be 0 or 1 and b could be 0 or 1 and expected could be either too. $monitor would not know the what the stable number is.