Answer from cs61c-bx (Tuan Ha 16989532) for Question 4
Without #10, all statements will happen at the beginning of the simulation which will cause undefined result. We want the statement from line 3 happen first, then after 10ns, the statment from line 4 will run which cause a change in the value of a, b and expected. Since in Verilog, the only way to simulate changes in time is using #10, omitting #10 will give undefined results.