Answer from cs61c-cb (minh uyen nguyen 16765774) for Question 4
In the first "initial", there is no "#n"s (simuated time).  Because everything in Verilog happens at a particular time (or simulated time).  Without specifying the advanced time of each simulation, all the statements in this section will be executed at the same time, causing undefined results.

Time does not move along until we do something to advance it.  And without advancing time, no useful simulation can happen.