Answer from cs61c-cf (Aspandiar Dahmubed 16812056) for Question 4
 // #10 omitted!!
At the same time that a, b and expected get assigned their values, due to the omission of the delay, the next Verilog instruction that changes their value again would kick in too. Monitor outputs results everytime the values of any of the variables changes. In this case, the values would change all the time (without even a delay!!) and that could cause the program to crash.