Answer from cs61c-el (David Tung 16479725) for Question 4
The problems would appear if there is delay in the module that s, a, and b are ports of.  If that module has a delay, say of 5 ns, then before it can finish calculating what its output should be for the first set, new input is given to it.  Since the input is changed in the middle of the process, and since a and b are flipped, it seems likely that the process will head down an opposite branch than it was first intended.  SInce $monitor displays any changes, it will show some undefined output because what was supposed to be the output of the first set of arguments has not yet been totally defined when it is changed.