Answer from cs61c-ew (Joo-Rak Son 16103505) for Question 4
Undefined result in Verilog is indicated with the symbol "x". The output of this code is undefined because the lines "s=0; a=0; b=1; expected=0;" and "a=1; b=0; expected=1;" would be run simultaneously. Since a and b cannot be both 0 and 1 at the same time, these variables are undefined.