Your friend says the following Verilog code would cause "undefined
results."

initial
  begin
    s=0; a=0; b=1; expected=0;
    a=1; b=0; expected=1;       // #10 omitte

initial
  $monitor (
    "select=%b in0=%b in1=%b out=%b expected=%b time=%d", 
    s, a, b, f, expected, $time);

Elaborate on what the undefined results might be, and the reasons they
might appear as you describe.