Quiz submission record for quiz4-2-1 at Tue Jul 13 21:10:33 2004:

Your Answer for Question 1:
In C, the arguments(only names in caller function are required) are placed inside parenthesis following the name of the function. The order of the arguments must be the same as the one in the function declaration.

In Verilog, the arguments (both the names in the caller and callee functions are included) are placed in the parenthesis. Using the dot notation, the order of the arguments are not important.

Your Answer for Question 2:
initial begin CLK=1 b0; 
forever 
#2 CLK = ~CLK; 
end

Your Answer for Question 3:

1 wire to get AB
1 wire to get C_bar
1 wire to get ABC_bar

3 wires to get ACB_bar

1 wires for OR

Total: 7 wires

Your Answer for Question 4:
If we include #10, 
then,s=0; a=0; b=1; expected=0 at time 
and a=1; b=0; expected=1 at time 10.

If we omit the 10, then a=0 and a=1 at the same time, so there will be "undefined results".


Your unique submission ID is quiz4-2-1-cs61c-ac-1089778233-2163.