Quiz submission record for quiz4-2-1 at Wed Jul 14 02:00:30 2004:

Your Answer for Question 1:
I don't really understand this question. But i think in C we pass the argument value from caller to callee. In Verilog, we just pass the high/low signal to the function arguments.

Your Answer for Question 2:
initial
   begin
      CLK=1'b0;
      forever
         #2 CLK = ~CLK;
      end






Your Answer for Question 3:
we will need 4 wires. since we have cbar and bbar, we need 2 more wires beside wire for a, b and c. 

Your Answer for Question 4:
The undefined results would be time and out because i think we omitted the delay time. 


Your unique submission ID is quiz4-2-1-cs61c-ad-1089795630-1879.