Quiz submission record for quiz4-2-1 at Tue Jul 13 23:37:47 2004:

Your Answer for Question 1:
The arguments of functions are normally associated with the function in C, but in Verilog you use modules to process instructions and commands. You define input and outputs associated with the module at hand. You also define three additional signals.

Your Answer for Question 2:
module clk;
reg a, b, s;
wire f;
reg expected;
clk myCLK (.select(s), .in0(a), .in1(b), .out(f));
initial
begin
#0 s=0; a=0; b=1; expected=0;
#10 a=1; b=0; expected=1;
#10 s=1; a=0; b=1; expected=1;
#10 $finish;
end
initial
$monitor(
"select=%b in0=%b in1=%b out=%b, expected out=%b time=%d",
s, a, b, f, expected, $time);
endmodule // testclk

Your Answer for Question 3:
Three wires for the first part, and three wires for the second part. Then you need three more wires for the last part, and then two for the two not operations, amking a grand total of 11 wires.

Your Answer for Question 4:
This code looks problematic in that it omitted #10. It might cause undesirable behavior in the $monitor clause, with the f being undefined. 


Your unique submission ID is quiz4-2-1-cs61c-ah-1089787067-3163.