Quiz submission record for quiz4-2-1 at Wed Jul 14 00:03:22 2004:

Your Answer for Question 1:
C programmer will initialize a function with the argument types and variables. The position of the argument matters which argument is sent from caller to callee. For example, foo (int x, int y) the caller calls foo by foo(1, 4) the 1 gets binded to x and 4 gets binded to y. In verilog, however, even after the function declaration. arguments are supplied with the . notation. For example, for foo (x, y, z) the caller has to say foo (.y(5), .x(1), .z(3)) in order to bind 5 to argument y 1 to argument x and 3 to argument 3. In Verilog order does not matter.

Your Answer for Question 2:
initial
   begin
    CLK = 1'b0;
     forever
       #2 CLK = ~CLK;
   end

Your Answer for Question 3:
not(c0, C)
and(b0, B, c0)
and(a0, b0, A)
not(b1, B)
and(c1, C, b1)
and(a1, A, b1)
or(E, a1, a0)

wire c0, b0, a0, b1, c1, a1

6 wires total a wire is needed for each logic output except for the last one which is the or because the output is just E

Your Answer for Question 4:
Since there is no #10 that means that both lines are excuted at the same time. In Verilog, time is counted by # otherwise all lines start at the same time at the beginning. So the results are undefined because at the beginning both lines start excuting the code and a could be 0 or 1 and b could be 0 or 1 and expected could be either too. $monitor would not know the what the stable number is. 


Your unique submission ID is quiz4-2-1-cs61c-aj-1089788602-2804.