Quiz submission record for quiz4-2-1 at Wed Jul 14 00:29:04 2004:

Your Answer for Question 1:
For C, they are just put inside parenthesis and each argument seperated by a comma. To call a function foo with the arguments 1 and 2, simply call by: foo(1, 2). In verilog it is very similar, except the actual name of the parameter is requried. So if in C the prototype were foo( int x, int y), in verilog it would be typed foo(.x(1), .y(2));. Also the return value is named so it to be more complete it would be:

result foo(.x(1), .y(2));

Your Answer for Question 2:
module clock
     inital
       begin
          CLK = 1'b0;
          forever
              #2 CLK = ~CLK;
        end
endmodule

Your Answer for Question 3:
4 wires will be needed. There will be 2 because of the two inverters that will be needed between the AND and the input. Another 2 will be the outputs from the ANDs and the inputs to the OR.

Your Answer for Question 4:
In this you are trying to set a, b, and expected to two different values each at the same time. Since there is no delay between the two definitions (the first two lines after begin) it is unsure what the value will be.


Your unique submission ID is quiz4-2-1-cs61c-al-1089790144-978.