Quiz submission record for quiz4-2-1 at Wed Jul 14 03:31:02 2004:

Your Answer for Question 1:
in C, the variables are typed in the callee only.  For Verilog, both caller and callee type their input (In0(a)...)

in C, the arguments are read in the order they come in in the caller in the same order the callee will read them.
For Verilog, since the arguments are typed specifically, (In1, In2, etc), the name is what specifies which argument is passed in

Your Answer for Question 2:
module CLK;
    reg clock;

initial
    begin
        #4 if(clock) clock = 0; else clock = 1;
    end

Your Answer for Question 3:
distribute to E = A(Bnot(C)+not(B)C)

simplifies futher to A . (not(B . C) . (B + C))
     an XOR, as the Bnot(C)+not(B)C is only true iff one of the inputs is true, not two

two wires to (B+C)
two wires to not(B.C)
two wires to (B+C) . not(B.C) 
two wires to A . (stuff)
one wire to E

nine wires are needed

Your Answer for Question 4:
Since there is no delay, the values do not change from s = 0, as the clock does not rise w/o delay


Your unique submission ID is quiz4-2-1-cs61c-am-1089801062-756.