Quiz submission record for quiz4-2-1 at Tue Jul 13 22:44:24 2004:

Your Answer for Question 1:
In C, the order of the parameters directly dictates which arguments obtain what value, whereas in verilog, the "." notation allows the arguments to be passed in an arbitrary order, using the name of the argument in the call to the function.

Your Answer for Question 2:
input CLK

initial 
   begin
     CLK = 1 'b0;
     forever
        #4 CLK = ~CLK;
   end

Your Answer for Question 3:
A(B.not(C) + C.not(B))
1 wire to connect the each of the products inside the parens to the OR gate and then one wire to connect the result of that to the AND gate with A

3 wires

Your Answer for Question 4:
There is no time step included in the code, so essentially everything is supposed to occur at once, and it is impossible for it to have two expected values at the same time


Your unique submission ID is quiz4-2-1-cs61c-an-1089783864-961.