Quiz submission record for quiz4-2-1 at Tue Jul 13 23:35:09 2004:

Your Answer for Question 1:
These arguments are put in parenthesis in both c and verilog. In C you have a function name followed by a parenthesis with an argument list, whereas in verilog you name the inputs and outputs and put the args in parentheses after the ".name".

Your Answer for Question 2:
initial
  begin
    CLK = 1'b0;
    forever
      #4 CLK = ~CLK;
  end

Your Answer for Question 3:
Two wires will be necessary. One will be needed at the output of each AND gate (there are 2 here).

Your Answer for Question 4:
A, b, and expected are all initialized twice depending on if the second value get to through, the output may or may not always be the first values, the second values our a mixture of both.


Your unique submission ID is quiz4-2-1-cs61c-ap-1089786909-2088.