Quiz submission record for quiz4-2-1 at Tue Jul 13 22:38:07 2004:

Your Answer for Question 1:
In C, arguments of a function copy values of the caller by value. so a change in the args in the function are not visible outside the function.

In Verilog, any change in one module is immediately visible in it's counterpart in the other module

Your Answer for Question 2:
initial
  begin
    CLK=1’b0;
    forever
    #2 CLK = ˜CLK;
end

CLK changes from 0 to 1 after 2 ns and back to 0 after another 2 ns making the oscillation period= 4ns

Your Answer for Question 3:
not(c) - one wire
A.B - 2 wires (one to connect them and one to connect to (not c))
not(b)- one wire
A.C- 2 wires (one to connect them and one to connect it to not(b))
one wire to connect AB(not c) to AC(not b) and do the OR function

Your Answer for Question 4:
As mentioned, no timelag has been specified. From the tutorial,
The important thing to remember about Verilog is that time does not move along until we do something to advance it.

As no delay has been specified, verilog will try to execute all the instructions simultaneously.
the instructions
a=0 and a=1 are executed at the same instant, which results in undefined results. 


Your unique submission ID is quiz4-2-1-cs61c-aq-1089783487-1893.