Quiz submission record for quiz4-2-1 at Wed Jul 14 01:08:11 2004:

Your Answer for Question 1:
the arguments of a C function go in the order provided in the definition of the function.

the arguments of a Verilog module can either go in the order it was defined in or you can specify which argument is used for each port.

Your Answer for Question 2:
initial
  begin
    CLK = 1'b0;
    forever
      #2  CLK = ~CLK;
  end

Your Answer for Question 3:
6

and(w0,A,B)
not(s0,C)
and(w1,w0,s0)

and(w2,A,C)
not(s1,B)
and(w3,w2,s1)

or(E,w1,w3)


Your Answer for Question 4:
This creates undefined results because there is no delay between the statements so both statements occur at the same time at the start, which is undefined.


Your unique submission ID is quiz4-2-1-cs61c-at-1089792491-1574.