Quiz submission record for quiz4-2-1 at Wed Jul 14 09:22:50 2004: Your Answer for Question 1: First you need to instantiate the module and give it a local name: “mux2 myMux ...”The local name is used to distinguish from other instances of mux2 that we might make. After that you have a list of connections. The syntax used here lists the ports of mux2 in arbitrary order, each one preceded by a “.”, and followed by the name of a local signal in parentheses. Verilog also allows making connections between local signals and module ports by simply listing the names of the local signals in the order that the ports where defined in the module header. However, the “dot” form because it allows you to list the ports in any order, making it easier to make changes later, and provides a reminder of exactly which signal is being connected to what port. Your Answer for Question 2: module clk; reg CLK; initial begin CLK=1 b0; forever #2 CLK = CLK; end endmodule Your Answer for Question 3: Wires are needed to connect logic gates together. ABnot(C) requires two wires. ACnot(B) also requires two wires. and the OR of both these results requires 1 wire. So altogether, 5 wires are necessary. Your Answer for Question 4: The cause for undefined results, is if everything is run at the same time, or basically if there is no delay inbetween commands. In the code above, you set a=0 and b=1 in the first line, and a=1,b=0 in the second line. But since it is all executed at the same time, a system might get the command a=0, b=0 rather than the lines above. This could cause unexpected results Your unique submission ID is quiz4-2-1-cs61c-av-1089822170-1890.