Quiz submission record for quiz4-2-1 at Wed Jul 14 09:20:44 2004:

Your Answer for Question 1:
In C, the callee is a function method with arbitrary arguments (i.e. int square(int x) where x is an arbitrary int).  The caller calls the callee by passing an argument with which the callee will need to operate (i.e. the caller may call square(5)).  Interestingly, Verilog "sorta" combines these two steps - such as seen in the testbench for mux2.  In Verilog, a module is declared much like C with arbitrary arguments (i.e. module mux2(in0, in1, select, out)) - however, when a module is instantiated and thus calls the module callee, the caller testmux passes the ports and the name of the local signal (i.e. myMux(.select(s)...) where .select is the port and s is the local name).

Your Answer for Question 2:
initial
  begin
     CLK=1'b0;
     forever
     #2 CLK = ~CLK;
  end

Your Answer for Question 3:
Since the equation simplifies to E = A(BnotC + CnotB), you need 3 AND gates and 1 OR gate.  The first AND gate produces BnotC and the second CnotB.  These are then passed through an OR gate to produce (BnotC + CnotB).  Finally that is passed through the third AND gate with A to produce E = ABnot(C) + ACnot(B).  Thus, there are 8 wires needed: 2 to each of the gates' inputs (and 9 wires if you include the output).

Your Answer for Question 4:
The undefined results would be because the #10 is omitted.  That is, there is no delay between when the two clauses in the "begin" section will run, thus there may be overlap.  More specifically, each clause needs to run uninterrupted in order to see if it produces accurate results.  Thus, if the first clause is running and the second one begins before the first is finished, it will change the values in the registers and possibly skewer the results of the first clause.


Your unique submission ID is quiz4-2-1-cs61c-ax-1089822044-1770.