Quiz submission record for quiz4-2-1 at Wed Jul 14 10:47:33 2004:

Your Answer for Question 1:
In C arguments are passed as an ordered list, and arguments are associated by the order they're declared and passed in. 

The same is done in Verilog, instead of arguments, modules have inputs and output pins, but they're also passed as an ordered list.

Your Answer for Question 2:
module clock(CLK);
initial
begin
CLK=1’b0;
forever
#5 CLK = ˜CLK;
end

Your Answer for Question 3:
4 wires,
two to connect to the two inputs of the or gate, and one each to convert a two pairs of and gates into two 3-input and gates.

Your Answer for Question 4:
a b and expected are set two to values at the same time. unless a time frame is specified verilog statements are executed simultaneously. Setting a signal to different values simultaneously causes an undefined result.


Your unique submission ID is quiz4-2-1-cs61c-ay-1089827253-2454.