Quiz submission record for quiz4-2-1 at Tue Jul 13 23:23:52 2004:

Your Answer for Question 1:
C: order of arguments;
Verilog: either order or through 
      .original_arg_name(local_arg_name)


Your Answer for Question 2:
initial
   begin
       CLK = l'b0;
       forever
           #2 CLK = ~CLK
   end

Your Answer for Question 3:
6 wires;

We have 7 gates (AND, OR, NOT) and, therefore,  6 wires connecting them.

Your Answer for Question 4:
We do not increment or in any other way take care of time, so all of the statements will occur at the same time causing undefined results. 


Your unique submission ID is quiz4-2-1-cs61c-bc-1089786232-116.