Quiz submission record for quiz4-2-1 at Tue Jul 13 21:58:38 2004:

Your Answer for Question 1:
The callee copys the arguments of caller.

Caller{
    Callee(1,2);
}

void Callee(int a , int b){
}

a is 1, b is 2.
 
In Verilog, Caller links each arguments for callee like followings

module caller;
    reg a,b,s
    wire f;
    callee mycallee(.first(s), .second(a), .third(b)  
                    , .fourth(d));
endmodule

..

module callee(first, second, third, fourth);
...
endmodule

Your Answer for Question 2:
initial
  begin
    CLK=1'b0
    forever
      #5 CLK= ~CLK
  end

Your Answer for Question 3:
each OR and AND needs two wires, and NOT increase the number of wire by 1.
there is 4 ANDs, 1 ORs, 2 NOTs and output. so 13 wires will be needed.

Your Answer for Question 4:
s, a, b , f, expected is undefined -> we must define like 'reg s, a, b;'





Your unique submission ID is quiz4-2-1-cs61c-bd-1089781118-2067.