Quiz submission record for quiz4-2-1 at Wed Jul 14 00:17:52 2004:

Your Answer for Question 1:
In C, the arguments are simply listed in the first line of the functino after the name of the function with a declaration of their type.  When the function is called, the arguments are passed within parentheses after the function name.  In Verilog, the declaration is made similarly, but the types are not declared, and when the function is called, the connection between the arguments is made by calling the name of the argument within the callee preceded by a period, and then following it with the previous variable name in parentheses.

Your Answer for Question 2:
module CLK
  output CLK;
  always #2 CLK = ~CLK;
endmodule

Your Answer for Question 3:
A^(CxorB)

this would take four wires, one for the and, one for each not operation within the xor, and one for the or operation in the xor.

Your Answer for Question 4:
because there is no delay to deal with the clock cycle because the #10 was omitted, it is hard to say exactly how the sequentiality of the operation might continue, as it will try to run instantaneously.


Your unique submission ID is quiz4-2-1-cs61c-bg-1089789472-151.