Quiz submission record for quiz4-2-1 at Tue Jul 13 20:39:04 2004:

Your Answer for Question 1:
C programmer associtae the arguments of a function at the caller with the callee by passing values to the callee function. 
In Verilog, the arguments are passed by "addresses", e.g., the actual arguments are passed.

Your Answer for Question 2:
initial
begin
CLK=1’b0;
forever
#2 CLK = ˜CLK;
end

Your Answer for Question 3:
AB(not C) --> (AB) (not C) --> 1 wire w0 for AND (AB), 1 wire w1 for (not C) and 1 wire w2 for (AB).(not C)
AC(not B) --> 3 more wires.
So there are a total of 3+3+1 = 7 wires. 

Your Answer for Question 4:
Without #10, all statements will happen at the beginning of the simulation which will cause undefined result. We want the statement from line 3 happen first, then after 10ns, the statment from line 4 will run which cause a change in the value of a, b and expected. Since in Verilog, the only way to simulate changes in time is using #10, omitting #10 will give undefined results.


Your unique submission ID is quiz4-2-1-cs61c-bx-1089776344-876.