Quiz submission record for quiz4-2-1 at Wed Jul 14 10:43:47 2004:

Your Answer for Question 1:
C passes those arguments as actual parameters

Verilog uses submodules within modules

Your Answer for Question 2:
initial
   begin
      CLK= 1'b0;
      forever
        #4 CLK= ~CLK;
   end

Your Answer for Question 3:
4 wires: 2 to connect 2-AND pairs, 2 to connect 2 ANDs with OR

Your Answer for Question 4:
Since the clock is not incremented, and the simulation is not ended with "#n finish," there will be undefined result


Your unique submission ID is quiz4-2-1-cs61c-by-1089827027-783.