Quiz submission record for quiz4-2-1 at Wed Jul 14 10:26:45 2004:

Your Answer for Question 1:
they are passed in parenthesis to the callee. it is done the same way in Verilog:

mux2 (.out (o), .in (a)) etc..

Your Answer for Question 2:

module clock;
  #1 a=1
  #1 a=0
  #1 a=1
  #1 a=0
endmodule

Your Answer for Question 3:

a wire from A, B, C to the first and, one wire from A, B, C to the second and, another wire to the or

Your Answer for Question 4:
because you are setting the values all at the same time, you don't know what will happen first or second. you need the #10 in there to force things to happen sequentially


Your unique submission ID is quiz4-2-1-cs61c-ca-1089826005-2029.